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5fa2daaa VG |
1 | /* |
2 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /* | |
10 | * Device tree for AXC003 CPU card: HS38x UP configuration | |
11 | */ | |
12 | ||
2e8cd938 VG |
13 | /include/ "skeleton_hs.dtsi" |
14 | ||
5fa2daaa VG |
15 | / { |
16 | compatible = "snps,arc"; | |
f862b315 EP |
17 | #address-cells = <2>; |
18 | #size-cells = <2>; | |
5fa2daaa VG |
19 | |
20 | cpu_card { | |
21 | compatible = "simple-bus"; | |
22 | #address-cells = <1>; | |
23 | #size-cells = <1>; | |
24 | ||
f862b315 | 25 | ranges = <0x00000000 0x0 0xf0000000 0x10000000>; |
5fa2daaa | 26 | |
f6a09bac | 27 | input_clk: input-clk { |
b3d6aba8 VG |
28 | #clock-cells = <0>; |
29 | compatible = "fixed-clock"; | |
f6a09bac EP |
30 | clock-frequency = <33333333>; |
31 | }; | |
32 | ||
33 | core_clk: core-clk@80 { | |
34 | compatible = "snps,axs10x-arc-pll-clock"; | |
35 | reg = <0x80 0x10>, <0x100 0x10>; | |
36 | #clock-cells = <0>; | |
37 | clocks = <&input_clk>; | |
fbd1cec5 EP |
38 | |
39 | /* | |
40 | * Set initial core pll output frequency to 90MHz. | |
41 | * It will be applied at the core pll driver probing | |
42 | * on early boot. | |
43 | */ | |
44 | assigned-clocks = <&core_clk>; | |
45 | assigned-clock-rates = <90000000>; | |
b3d6aba8 VG |
46 | }; |
47 | ||
9ba7648c | 48 | core_intc: archs-intc@cpu { |
5fa2daaa VG |
49 | compatible = "snps,archs-intc"; |
50 | interrupt-controller; | |
51 | #interrupt-cells = <1>; | |
52 | }; | |
53 | ||
54 | /* | |
55 | * this GPIO block ORs all interrupts on CPU card (creg,..) | |
56 | * to uplink only 1 IRQ to ARC core intc | |
57 | */ | |
58 | dw-apb-gpio@0x2000 { | |
59 | compatible = "snps,dw-apb-gpio"; | |
60 | reg = < 0x2000 0x80 >; | |
61 | #address-cells = <1>; | |
62 | #size-cells = <0>; | |
63 | ||
64 | ictl_intc: gpio-controller@0 { | |
65 | compatible = "snps,dw-apb-gpio-port"; | |
66 | gpio-controller; | |
67 | #gpio-cells = <2>; | |
68 | snps,nr-gpios = <30>; | |
69 | reg = <0>; | |
70 | interrupt-controller; | |
71 | #interrupt-cells = <2>; | |
9ba7648c | 72 | interrupt-parent = <&core_intc>; |
5fa2daaa VG |
73 | interrupts = <25>; |
74 | }; | |
75 | }; | |
76 | ||
77 | debug_uart: dw-apb-uart@0x5000 { | |
78 | compatible = "snps,dw-apb-uart"; | |
79 | reg = <0x5000 0x100>; | |
80 | clock-frequency = <33333000>; | |
81 | interrupt-parent = <&ictl_intc>; | |
82 | interrupts = <2 4>; | |
83 | baud = <115200>; | |
84 | reg-shift = <2>; | |
85 | reg-io-width = <4>; | |
86 | }; | |
87 | ||
88 | arcpct0: pct { | |
89 | compatible = "snps,archs-pct"; | |
90 | #interrupt-cells = <1>; | |
9ba7648c | 91 | interrupt-parent = <&core_intc>; |
5fa2daaa VG |
92 | interrupts = <20>; |
93 | }; | |
94 | }; | |
95 | ||
678c8110 EP |
96 | /* |
97 | * Mark DMA peripherals connected via IOC port as dma-coherent. We do | |
98 | * it via overlay because peripherals defined in axs10x_mb.dtsi are | |
99 | * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so | |
100 | * only AXS103 board has HW-coherent DMA peripherals) | |
101 | * We don't need to mark pgu@17000 as dma-coherent because it uses | |
102 | * external DMA buffer located outside of IOC aperture. | |
103 | */ | |
104 | axs10x_mb { | |
105 | ethernet@0x18000 { | |
106 | dma-coherent; | |
107 | }; | |
108 | ||
109 | ehci@0x40000 { | |
110 | dma-coherent; | |
111 | }; | |
112 | ||
113 | ohci@0x60000 { | |
114 | dma-coherent; | |
115 | }; | |
116 | ||
117 | mmc@0x15000 { | |
118 | dma-coherent; | |
119 | }; | |
120 | }; | |
121 | ||
5fa2daaa | 122 | /* |
09074950 VG |
123 | * The DW APB ICTL intc on MB is connected to CPU intc via a |
124 | * DT "invisible" DW APB GPIO block, configured to simply pass thru | |
125 | * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c) | |
126 | * | |
127 | * So here we mimic a direct connection betwen them, ignoring the | |
128 | * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core) | |
129 | * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO) | |
5fa2daaa VG |
130 | * |
131 | * This intc actually resides on MB, but we move it here to | |
132 | * avoid duplicating the MB dtsi file given that IRQ from | |
133 | * this intc to cpu intc are different for axs101 and axs103 | |
134 | */ | |
135 | mb_intc: dw-apb-ictl@0xe0012000 { | |
136 | #interrupt-cells = <1>; | |
137 | compatible = "snps,dw-apb-ictl"; | |
f862b315 | 138 | reg = < 0x0 0xe0012000 0x0 0x200 >; |
5fa2daaa | 139 | interrupt-controller; |
9ba7648c | 140 | interrupt-parent = <&core_intc>; |
5fa2daaa VG |
141 | interrupts = < 24 >; |
142 | }; | |
143 | ||
144 | memory { | |
5fa2daaa | 145 | device_type = "memory"; |
9ed68785 | 146 | /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ |
f862b315 EP |
147 | reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */ |
148 | 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */ | |
5fa2daaa | 149 | }; |
cb2ad5e5 AB |
150 | |
151 | reserved-memory { | |
f862b315 EP |
152 | #address-cells = <2>; |
153 | #size-cells = <2>; | |
cb2ad5e5 AB |
154 | ranges; |
155 | /* | |
156 | * Move frame buffer out of IOC aperture (0x8z-0xAz). | |
157 | */ | |
158 | frame_buffer: frame_buffer@be000000 { | |
159 | compatible = "shared-dma-pool"; | |
f862b315 | 160 | reg = <0x0 0xbe000000 0x0 0x2000000>; |
cb2ad5e5 AB |
161 | no-map; |
162 | }; | |
163 | }; | |
5fa2daaa | 164 | }; |