Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
cfdbc2e1 VG |
2 | # |
3 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
4 | # | |
cfdbc2e1 VG |
5 | |
6 | config ARC | |
7 | def_bool y | |
c4c9a040 | 8 | select ARC_TIMERS |
f73c9045 | 9 | select ARCH_HAS_DMA_PREP_COHERENT |
c27d0e90 | 10 | select ARCH_HAS_PTE_SPECIAL |
347cb6af | 11 | select ARCH_HAS_SETUP_DMA_OPS |
6c3e71dd CH |
12 | select ARCH_HAS_SYNC_DMA_FOR_CPU |
13 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE | |
2a440168 | 14 | select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
942fa985 | 15 | select ARCH_32BIT_OFF_T |
10916706 | 16 | select BUILDTIME_TABLE_SORT |
4adeefe1 | 17 | select CLONE_BACKWARDS |
69fbd098 | 18 | select COMMON_CLK |
f73c9045 | 19 | select DMA_DIRECT_REMAP |
ce636527 | 20 | select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) |
cfdbc2e1 VG |
21 | select GENERIC_CLOCKEVENTS |
22 | select GENERIC_FIND_FIRST_BIT | |
23 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
24 | select GENERIC_IRQ_SHOW | |
c1678ffc | 25 | select GENERIC_PCI_IOMAP |
cfdbc2e1 | 26 | select GENERIC_PENDING_IRQ if SMP |
bf287607 | 27 | select GENERIC_SCHED_CLOCK |
cfdbc2e1 | 28 | select GENERIC_SMP_IDLE_THREAD |
f46121bd | 29 | select HAVE_ARCH_KGDB |
547f1125 | 30 | select HAVE_ARCH_TRACEHOOK |
bd71c453 | 31 | select HAVE_COPY_THREAD_TLS |
c27d0e90 | 32 | select HAVE_DEBUG_STACKOVERFLOW |
9fbea0b7 | 33 | select HAVE_DEBUG_KMEMLEAK |
5464d03d | 34 | select HAVE_FUTEX_CMPXCHG if FUTEX |
4368902b | 35 | select HAVE_IOREMAP_PROT |
c27d0e90 VG |
36 | select HAVE_KERNEL_GZIP |
37 | select HAVE_KERNEL_LZMA | |
4d86dfbb VG |
38 | select HAVE_KPROBES |
39 | select HAVE_KRETPROBES | |
eb1357d9 | 40 | select HAVE_MOD_ARCH_SPECIFIC |
769bc1fd | 41 | select HAVE_OPROFILE |
9c57564e | 42 | select HAVE_PERF_EVENTS |
1b0ccb8a | 43 | select HANDLE_DOMAIN_IRQ |
999159a5 | 44 | select IRQ_DOMAIN |
cfdbc2e1 | 45 | select MODULES_USE_ELF_RELA |
999159a5 VG |
46 | select OF |
47 | select OF_EARLY_FLATTREE | |
20f1b79d | 48 | select PCI_SYSCALL if PCI |
82385732 | 49 | select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING |
f091d5a4 | 50 | select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 |
cfdbc2e1 | 51 | |
eb277739 EP |
52 | config ARCH_HAS_CACHE_LINE_SIZE |
53 | def_bool y | |
54 | ||
0dafafc3 VG |
55 | config TRACE_IRQFLAGS_SUPPORT |
56 | def_bool y | |
57 | ||
58 | config LOCKDEP_SUPPORT | |
59 | def_bool y | |
60 | ||
cfdbc2e1 VG |
61 | config SCHED_OMIT_FRAME_POINTER |
62 | def_bool y | |
63 | ||
64 | config GENERIC_CSUM | |
65 | def_bool y | |
66 | ||
26f9d5fd | 67 | config ARCH_DISCONTIGMEM_ENABLE |
d140b9bf | 68 | def_bool n |
26f9d5fd | 69 | |
cfdbc2e1 VG |
70 | config ARCH_FLATMEM_ENABLE |
71 | def_bool y | |
72 | ||
73 | config MMU | |
74 | def_bool y | |
75 | ||
ce816fa8 | 76 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
77 | def_bool y |
78 | ||
79 | config GENERIC_CALIBRATE_DELAY | |
80 | def_bool y | |
81 | ||
82 | config GENERIC_HWEIGHT | |
83 | def_bool y | |
84 | ||
44c8bb91 VG |
85 | config STACKTRACE_SUPPORT |
86 | def_bool y | |
87 | select STACKTRACE | |
88 | ||
fe6c1b86 VG |
89 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
90 | def_bool y | |
91 | depends on ARC_MMU_V4 | |
92 | ||
cfdbc2e1 VG |
93 | menu "ARC Architecture Configuration" |
94 | ||
93ad700d | 95 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 96 | |
072eb693 | 97 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 98 | source "arch/arc/plat-axs10x/Kconfig" |
cfdbc2e1 | 99 | #New platform adds here |
96665789 | 100 | source "arch/arc/plat-eznps/Kconfig" |
a518d637 | 101 | source "arch/arc/plat-hsdk/Kconfig" |
93ad700d | 102 | |
53d98958 | 103 | endmenu |
cfdbc2e1 | 104 | |
1f6ccfff VG |
105 | choice |
106 | prompt "ARC Instruction Set" | |
b7cc40c3 | 107 | default ISA_ARCV2 |
1f6ccfff VG |
108 | |
109 | config ISA_ARCOMPACT | |
110 | bool "ARCompact ISA" | |
fff7fb0b | 111 | select CPU_NO_EFFICIENT_FFS |
1f6ccfff VG |
112 | help |
113 | The original ARC ISA of ARC600/700 cores | |
114 | ||
65bfbcdf VG |
115 | config ISA_ARCV2 |
116 | bool "ARC ISA v2" | |
c4c9a040 | 117 | select ARC_TIMERS_64BIT |
65bfbcdf VG |
118 | help |
119 | ISA for the Next Generation ARC-HS cores | |
1f6ccfff VG |
120 | |
121 | endchoice | |
122 | ||
cfdbc2e1 VG |
123 | menu "ARC CPU Configuration" |
124 | ||
125 | choice | |
126 | prompt "ARC Core" | |
1f6ccfff VG |
127 | default ARC_CPU_770 if ISA_ARCOMPACT |
128 | default ARC_CPU_HS if ISA_ARCV2 | |
129 | ||
130 | if ISA_ARCOMPACT | |
cfdbc2e1 VG |
131 | |
132 | config ARC_CPU_750D | |
133 | bool "ARC750D" | |
14a0abfc | 134 | select ARC_CANT_LLSC |
cfdbc2e1 VG |
135 | help |
136 | Support for ARC750 core | |
137 | ||
138 | config ARC_CPU_770 | |
139 | bool "ARC770" | |
742f8af6 | 140 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
141 | help |
142 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
143 | This core has a bunch of cool new features: | |
144 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
9a18b5a4 | 145 | Shared Address Spaces (for sharing TLB entries in MMU) |
cfdbc2e1 VG |
146 | -Caches: New Prog Model, Region Flush |
147 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
148 | ||
9a18b5a4 | 149 | endif #ISA_ARCOMPACT |
1f6ccfff VG |
150 | |
151 | config ARC_CPU_HS | |
152 | bool "ARC-HS" | |
153 | depends on ISA_ARCV2 | |
154 | help | |
155 | Support for ARC HS38x Cores based on ARCv2 ISA | |
156 | The notable features are: | |
a5760db2 | 157 | - SMP configurations of up to 4 cores with coherency |
1f6ccfff VG |
158 | - Optional L2 Cache and IO-Coherency |
159 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
160 | auto stack switch, auto regfile save/restore) | |
161 | - MMUv4 (PIPT dcache, Huge Pages) | |
162 | - Instructions for | |
163 | * 64bit load/store: LDD, STD | |
164 | * Hardware assisted divide/remainder: DIV, REM | |
165 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
166 | * IRQ enable/disable: CLRI, SETI | |
167 | * pop count: FFS, FLS | |
168 | * SETcc, BMSKN, XBFU... | |
169 | ||
cfdbc2e1 VG |
170 | endchoice |
171 | ||
172 | config CPU_BIG_ENDIAN | |
173 | bool "Enable Big Endian Mode" | |
cfdbc2e1 VG |
174 | help |
175 | Build kernel for Big Endian Mode of ARC CPU | |
176 | ||
41195d23 | 177 | config SMP |
82fea5a1 | 178 | bool "Symmetric Multi-Processing" |
82fea5a1 | 179 | select ARC_MCIP if ISA_ARCV2 |
41195d23 | 180 | help |
82fea5a1 | 181 | This enables support for systems with more than one CPU. |
41195d23 VG |
182 | |
183 | if SMP | |
184 | ||
41195d23 | 185 | config NR_CPUS |
3aa4f80e NC |
186 | int "Maximum number of CPUs (2-4096)" |
187 | range 2 4096 | |
82fea5a1 VG |
188 | default "4" |
189 | ||
3971cdc2 VG |
190 | config ARC_SMP_HALT_ON_RESET |
191 | bool "Enable Halt-on-reset boot mode" | |
3971cdc2 VG |
192 | help |
193 | In SMP configuration cores can be configured as Halt-on-reset | |
194 | or they could all start at same time. For Halt-on-reset, non | |
a5760db2 | 195 | masters are parked until Master kicks them so they can start off |
3971cdc2 VG |
196 | at designated entry point. For other case, all jump to common |
197 | entry point and spin wait for Master's signal. | |
198 | ||
9a18b5a4 | 199 | endif #SMP |
41195d23 | 200 | |
3ce0fefc VG |
201 | config ARC_MCIP |
202 | bool "ARConnect Multicore IP (MCIP) Support " | |
203 | depends on ISA_ARCV2 | |
204 | default y if SMP | |
205 | help | |
206 | This IP block enables SMP in ARC-HS38 cores. | |
207 | It provides for cross-core interrupts, multi-core debug | |
208 | hardware semaphores, shared memory,.... | |
209 | ||
cfdbc2e1 VG |
210 | menuconfig ARC_CACHE |
211 | bool "Enable Cache Support" | |
212 | default y | |
213 | ||
214 | if ARC_CACHE | |
215 | ||
216 | config ARC_CACHE_LINE_SHIFT | |
217 | int "Cache Line Length (as power of 2)" | |
218 | range 5 7 | |
219 | default "6" | |
220 | help | |
221 | Starting with ARC700 4.9, Cache line length is configurable, | |
222 | This option specifies "N", with Line-len = 2 power N | |
223 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
224 | Linux only supports same line lengths for I and D caches. | |
225 | ||
226 | config ARC_HAS_ICACHE | |
227 | bool "Use Instruction Cache" | |
228 | default y | |
229 | ||
230 | config ARC_HAS_DCACHE | |
231 | bool "Use Data Cache" | |
232 | default y | |
233 | ||
234 | config ARC_CACHE_PAGES | |
235 | bool "Per Page Cache Control" | |
236 | default y | |
237 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
238 | help | |
239 | This can be used to over-ride the global I/D Cache Enable on a | |
240 | per-page basis (but only for pages accessed via MMU such as | |
241 | Kernel Virtual address or User Virtual Address) | |
242 | TLB entries have a per-page Cache Enable Bit. | |
243 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
244 | Global DISABLE + Per Page ENABLE won't work | |
245 | ||
4102b533 VG |
246 | config ARC_CACHE_VIPT_ALIASING |
247 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 248 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 | 249 | |
9a18b5a4 | 250 | endif #ARC_CACHE |
cfdbc2e1 | 251 | |
8b5850f8 VG |
252 | config ARC_HAS_ICCM |
253 | bool "Use ICCM" | |
254 | help | |
255 | Single Cycle RAMS to store Fast Path Code | |
8b5850f8 VG |
256 | |
257 | config ARC_ICCM_SZ | |
258 | int "ICCM Size in KB" | |
259 | default "64" | |
260 | depends on ARC_HAS_ICCM | |
261 | ||
262 | config ARC_HAS_DCCM | |
263 | bool "Use DCCM" | |
264 | help | |
265 | Single Cycle RAMS to store Fast Path Data | |
8b5850f8 VG |
266 | |
267 | config ARC_DCCM_SZ | |
268 | int "DCCM Size in KB" | |
269 | default "64" | |
270 | depends on ARC_HAS_DCCM | |
271 | ||
272 | config ARC_DCCM_BASE | |
273 | hex "DCCM map address" | |
274 | default "0xA0000000" | |
275 | depends on ARC_HAS_DCCM | |
276 | ||
cfdbc2e1 | 277 | choice |
1f6ccfff | 278 | prompt "MMU Version" |
cfdbc2e1 VG |
279 | default ARC_MMU_V3 if ARC_CPU_770 |
280 | default ARC_MMU_V2 if ARC_CPU_750D | |
d7a512bf | 281 | default ARC_MMU_V4 if ARC_CPU_HS |
cfdbc2e1 | 282 | |
c583ee4f VG |
283 | if ISA_ARCOMPACT |
284 | ||
cfdbc2e1 VG |
285 | config ARC_MMU_V1 |
286 | bool "MMU v1" | |
287 | help | |
288 | Orig ARC700 MMU | |
289 | ||
290 | config ARC_MMU_V2 | |
291 | bool "MMU v2" | |
292 | help | |
83fc61a5 | 293 | Fixed the deficiency of v1 - possible thrashing in memcpy scenario |
cfdbc2e1 VG |
294 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. |
295 | ||
296 | config ARC_MMU_V3 | |
297 | bool "MMU v3" | |
298 | depends on ARC_CPU_770 | |
299 | help | |
300 | Introduced with ARC700 4.10: New Features | |
301 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
302 | Shared Address Spaces (SASID) | |
303 | ||
c583ee4f VG |
304 | endif |
305 | ||
d7a512bf VG |
306 | config ARC_MMU_V4 |
307 | bool "MMU v4" | |
308 | depends on ISA_ARCV2 | |
309 | ||
cfdbc2e1 VG |
310 | endchoice |
311 | ||
312 | ||
313 | choice | |
314 | prompt "MMU Page Size" | |
315 | default ARC_PAGE_SIZE_8K | |
316 | ||
317 | config ARC_PAGE_SIZE_8K | |
318 | bool "8KB" | |
319 | help | |
320 | Choose between 8k vs 16k | |
321 | ||
322 | config ARC_PAGE_SIZE_16K | |
323 | bool "16KB" | |
450ed0db | 324 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
325 | |
326 | config ARC_PAGE_SIZE_4K | |
327 | bool "4KB" | |
450ed0db | 328 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
329 | |
330 | endchoice | |
331 | ||
37eda9df VG |
332 | choice |
333 | prompt "MMU Super Page Size" | |
334 | depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE | |
335 | default ARC_HUGEPAGE_2M | |
336 | ||
337 | config ARC_HUGEPAGE_2M | |
338 | bool "2MB" | |
339 | ||
340 | config ARC_HUGEPAGE_16M | |
341 | bool "16MB" | |
342 | ||
343 | endchoice | |
344 | ||
26f9d5fd VG |
345 | config NODES_SHIFT |
346 | int "Maximum NUMA Nodes (as a power of 2)" | |
3528f84f NC |
347 | default "0" if !DISCONTIGMEM |
348 | default "1" if DISCONTIGMEM | |
26f9d5fd VG |
349 | depends on NEED_MULTIPLE_NODES |
350 | ---help--- | |
351 | Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory | |
352 | zones. | |
353 | ||
4788a594 | 354 | config ARC_COMPACT_IRQ_LEVELS |
f45ba2bd | 355 | depends on ISA_ARCOMPACT |
60f2b4b8 | 356 | bool "Setup Timer IRQ as high Priority" |
41195d23 | 357 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
60f2b4b8 | 358 | depends on !SMP |
4788a594 | 359 | |
cfdbc2e1 VG |
360 | config ARC_FPU_SAVE_RESTORE |
361 | bool "Enable FPU state persistence across context switch" | |
cfdbc2e1 | 362 | help |
f45ba2bd VG |
363 | ARCompact FPU has internal registers to assist with Double precision |
364 | Floating Point operations. There are control and stauts registers | |
365 | for floating point exceptions and rounding modes. These are | |
366 | preserved across task context switch when enabled. | |
1f6ccfff | 367 | |
fbf8e13d VG |
368 | config ARC_CANT_LLSC |
369 | def_bool n | |
370 | ||
cfdbc2e1 VG |
371 | config ARC_HAS_LLSC |
372 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
373 | default y | |
14a0abfc | 374 | depends on !ARC_CANT_LLSC |
cfdbc2e1 VG |
375 | |
376 | config ARC_HAS_SWAPE | |
377 | bool "Insn: SWAPE (endian-swap)" | |
378 | default y | |
cfdbc2e1 | 379 | |
1f6ccfff VG |
380 | if ISA_ARCV2 |
381 | ||
76551468 EP |
382 | config ARC_USE_UNALIGNED_MEM_ACCESS |
383 | bool "Enable unaligned access in HW" | |
384 | default y | |
385 | select HAVE_EFFICIENT_UNALIGNED_ACCESS | |
386 | help | |
387 | The ARC HS architecture supports unaligned memory access | |
388 | which is disabled by default. Enable unaligned access in | |
389 | hardware and use software to use it | |
390 | ||
1f6ccfff VG |
391 | config ARC_HAS_LL64 |
392 | bool "Insn: 64bit LDD/STD" | |
393 | help | |
394 | Enable gcc to generate 64-bit load/store instructions | |
395 | ISA mandates even/odd registers to allow encoding of two | |
396 | dest operands with 2 possible source operands. | |
397 | default y | |
398 | ||
d05a76ab AB |
399 | config ARC_HAS_DIV_REM |
400 | bool "Insn: div, divu, rem, remu" | |
401 | default y | |
402 | ||
3d5e8012 | 403 | config ARC_HAS_ACCL_REGS |
4827d0cf | 404 | bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" |
af1fc5ba | 405 | default y |
3d5e8012 VG |
406 | help |
407 | Depending on the configuration, CPU can contain accumulator reg-pair | |
408 | (also referred to as r58:r59). These can also be used by gcc as GPR so | |
409 | kernel needs to save/restore per process | |
410 | ||
4827d0cf EP |
411 | config ARC_DSP_HANDLED |
412 | def_bool n | |
413 | ||
7321e2ea EP |
414 | config ARC_DSP_SAVE_RESTORE_REGS |
415 | def_bool n | |
416 | ||
4827d0cf EP |
417 | choice |
418 | prompt "DSP support" | |
419 | default ARC_DSP_NONE | |
420 | help | |
421 | Depending on the configuration, CPU can contain DSP registers | |
422 | (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). | |
423 | Bellow is options describing how to handle these registers in | |
424 | interrupt entry / exit and in context switch. | |
425 | ||
426 | config ARC_DSP_NONE | |
427 | bool "No DSP extension presence in HW" | |
428 | help | |
429 | No DSP extension presence in HW | |
430 | ||
431 | config ARC_DSP_KERNEL | |
432 | bool "DSP extension in HW, no support for userspace" | |
433 | select ARC_HAS_ACCL_REGS | |
434 | select ARC_DSP_HANDLED | |
435 | help | |
436 | DSP extension presence in HW, no support for DSP-enabled userspace | |
437 | applications. We don't save / restore DSP registers and only do | |
438 | some minimal preparations so userspace won't be able to break kernel | |
7321e2ea EP |
439 | |
440 | config ARC_DSP_USERSPACE | |
441 | bool "Support DSP for userspace apps" | |
442 | select ARC_HAS_ACCL_REGS | |
443 | select ARC_DSP_HANDLED | |
444 | select ARC_DSP_SAVE_RESTORE_REGS | |
445 | help | |
446 | DSP extension presence in HW, support save / restore DSP registers to | |
447 | run DSP-enabled userspace applications | |
f09d3174 EP |
448 | |
449 | config ARC_DSP_AGU_USERSPACE | |
450 | bool "Support DSP with AGU for userspace apps" | |
451 | select ARC_HAS_ACCL_REGS | |
452 | select ARC_DSP_HANDLED | |
453 | select ARC_DSP_SAVE_RESTORE_REGS | |
454 | help | |
455 | DSP and AGU extensions presence in HW, support save / restore DSP | |
456 | and AGU registers to run DSP-enabled userspace applications | |
4827d0cf EP |
457 | endchoice |
458 | ||
e494239a VG |
459 | config ARC_IRQ_NO_AUTOSAVE |
460 | bool "Disable hardware autosave regfile on interrupts" | |
461 | default n | |
462 | help | |
463 | On HS cores, taken interrupt auto saves the regfile on stack. | |
464 | This is programmable and can be optionally disabled in which case | |
465 | software INTERRUPT_PROLOGUE/EPILGUE do the needed work | |
466 | ||
9a18b5a4 | 467 | endif # ISA_ARCV2 |
1f6ccfff | 468 | |
cfdbc2e1 VG |
469 | endmenu # "ARC CPU Configuration" |
470 | ||
cfdbc2e1 | 471 | config LINUX_LINK_BASE |
9ed68785 | 472 | hex "Kernel link address" |
cfdbc2e1 VG |
473 | default "0x80000000" |
474 | help | |
475 | ARC700 divides the 32 bit phy address space into two equal halves | |
476 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
477 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
478 | Typically Linux kernel is linked at the start of untransalted addr, | |
479 | hence the default value of 0x8zs. | |
480 | However some customers have peripherals mapped at this addr, so | |
481 | Linux needs to be scooted a bit. | |
482 | If you don't know what the above means, leave this setting alone. | |
ff1c0b6a | 483 | This needs to match memory start address specified in Device Tree |
cfdbc2e1 | 484 | |
9ed68785 EP |
485 | config LINUX_RAM_BASE |
486 | hex "RAM base address" | |
487 | default LINUX_LINK_BASE | |
488 | help | |
489 | By default Linux is linked at base of RAM. However in some special | |
490 | cases (such as HSDK), Linux can't be linked at start of DDR, hence | |
491 | this option. | |
492 | ||
45890f6d VG |
493 | config HIGHMEM |
494 | bool "High Memory Support" | |
d140b9bf | 495 | select ARCH_DISCONTIGMEM_ENABLE |
45890f6d VG |
496 | help |
497 | With ARC 2G:2G address split, only upper 2G is directly addressable by | |
498 | kernel. Enable this to potentially allow access to rest of 2G and PAE | |
499 | in future | |
500 | ||
5a364c2a VG |
501 | config ARC_HAS_PAE40 |
502 | bool "Support for the 40-bit Physical Address Extension" | |
5a364c2a | 503 | depends on ISA_ARCV2 |
cf4100d1 | 504 | select HIGHMEM |
d4a451d5 | 505 | select PHYS_ADDR_T_64BIT |
5a364c2a VG |
506 | help |
507 | Enable access to physical memory beyond 4G, only supported on | |
508 | ARC cores with 40 bit Physical Addressing support | |
509 | ||
15ca68a9 | 510 | config ARC_KVADDR_SIZE |
83fc61a5 | 511 | int "Kernel Virtual Address Space size (MB)" |
15ca68a9 NC |
512 | range 0 512 |
513 | default "256" | |
514 | help | |
515 | The kernel address space is carved out of 256MB of translated address | |
516 | space for catering to vmalloc, modules, pkmap, fixmap. This however may | |
517 | not suffice vmalloc requirements of a 4K CPU EZChip system. So allow | |
518 | this to be stretched to 512 MB (by extending into the reserved | |
519 | kernel-user gutter) | |
520 | ||
080c3747 VG |
521 | config ARC_CURR_IN_REG |
522 | bool "Dedicate Register r25 for current_task pointer" | |
523 | default y | |
524 | help | |
525 | This reserved Register R25 to point to Current Task in | |
526 | kernel mode. This saves memory access for each such access | |
527 | ||
2e651ea1 | 528 | |
1736a56f | 529 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 530 | bool "Emulate unaligned memory access (userspace only)" |
2e651ea1 VG |
531 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
532 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 533 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
534 | help |
535 | This enables misaligned 16 & 32 bit memory access from user space. | |
536 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
537 | potential bugs in code | |
538 | ||
cfdbc2e1 VG |
539 | config HZ |
540 | int "Timer Frequency" | |
541 | default 100 | |
542 | ||
cbe056f7 VG |
543 | config ARC_METAWARE_HLINK |
544 | bool "Support for Metaware debugger assisted Host access" | |
cbe056f7 VG |
545 | help |
546 | This options allows a Linux userland apps to directly access | |
547 | host file system (open/creat/read/write etc) with help from | |
548 | Metaware Debugger. This can come in handy for Linux-host communication | |
549 | when there is no real usable peripheral such as EMAC. | |
550 | ||
cfdbc2e1 VG |
551 | menuconfig ARC_DBG |
552 | bool "ARC debugging" | |
553 | default y | |
554 | ||
aa6083ed VG |
555 | if ARC_DBG |
556 | ||
854a0d95 VG |
557 | config ARC_DW2_UNWIND |
558 | bool "Enable DWARF specific kernel stack unwind" | |
854a0d95 VG |
559 | default y |
560 | select KALLSYMS | |
561 | help | |
562 | Compiles the kernel with DWARF unwind information and can be used | |
563 | to get stack backtraces. | |
564 | ||
565 | If you say Y here the resulting kernel image will be slightly larger | |
566 | but not slower, and it will give very useful debugging information. | |
567 | If you don't debug the kernel, you can say N, but we may not be able | |
568 | to solve problems without frame unwind information | |
569 | ||
cfdbc2e1 VG |
570 | config ARC_DBG_TLB_PARANOIA |
571 | bool "Paranoia Checks in Low Level TLB Handlers" | |
cfdbc2e1 | 572 | |
f091d5a4 EP |
573 | config ARC_DBG_JUMP_LABEL |
574 | bool "Paranoid checks in Static Keys (jump labels) code" | |
575 | depends on JUMP_LABEL | |
576 | default y if STATIC_KEYS_SELFTEST | |
577 | help | |
578 | Enable paranoid checks and self-test of both ARC-specific and generic | |
579 | part of static keys (jump labels) related code. | |
aa6083ed VG |
580 | endif |
581 | ||
999159a5 VG |
582 | config ARC_BUILTIN_DTB_NAME |
583 | string "Built in DTB" | |
584 | help | |
585 | Set the name of the DTB to embed in the vmlinux binary | |
586 | Leaving it blank selects the minimal "skeleton" dtb | |
587 | ||
cfdbc2e1 VG |
588 | endmenu # "ARC Architecture Configuration" |
589 | ||
37eda9df VG |
590 | config FORCE_MAX_ZONEORDER |
591 | int "Maximum zone order" | |
592 | default "12" if ARC_HUGEPAGE_16M | |
593 | default "11" | |
594 | ||
996bad6c | 595 | source "kernel/power/Kconfig" |