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cfdbc2e1 VG |
1 | # |
2 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | # | |
4 | # This program is free software; you can redistribute it and/or modify | |
5 | # it under the terms of the GNU General Public License version 2 as | |
6 | # published by the Free Software Foundation. | |
7 | # | |
8 | ||
9 | config ARC | |
10 | def_bool y | |
c4c9a040 | 11 | select ARC_TIMERS |
58b04406 | 12 | select ARCH_HAS_DMA_COHERENT_TO_PFN |
c27d0e90 | 13 | select ARCH_HAS_PTE_SPECIAL |
347cb6af | 14 | select ARCH_HAS_SETUP_DMA_OPS |
6c3e71dd CH |
15 | select ARCH_HAS_SYNC_DMA_FOR_CPU |
16 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE | |
2a440168 | 17 | select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
942fa985 | 18 | select ARCH_32BIT_OFF_T |
f06d19e4 | 19 | select BUILDTIME_EXTABLE_SORT |
4adeefe1 | 20 | select CLONE_BACKWARDS |
69fbd098 | 21 | select COMMON_CLK |
ce636527 | 22 | select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) |
cfdbc2e1 VG |
23 | select GENERIC_CLOCKEVENTS |
24 | select GENERIC_FIND_FIRST_BIT | |
25 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
26 | select GENERIC_IRQ_SHOW | |
c1678ffc | 27 | select GENERIC_PCI_IOMAP |
cfdbc2e1 | 28 | select GENERIC_PENDING_IRQ if SMP |
bf287607 | 29 | select GENERIC_SCHED_CLOCK |
cfdbc2e1 | 30 | select GENERIC_SMP_IDLE_THREAD |
f46121bd | 31 | select HAVE_ARCH_KGDB |
547f1125 | 32 | select HAVE_ARCH_TRACEHOOK |
c27d0e90 | 33 | select HAVE_DEBUG_STACKOVERFLOW |
5464d03d | 34 | select HAVE_FUTEX_CMPXCHG if FUTEX |
4368902b | 35 | select HAVE_IOREMAP_PROT |
c27d0e90 VG |
36 | select HAVE_KERNEL_GZIP |
37 | select HAVE_KERNEL_LZMA | |
4d86dfbb VG |
38 | select HAVE_KPROBES |
39 | select HAVE_KRETPROBES | |
eb1357d9 | 40 | select HAVE_MOD_ARCH_SPECIFIC |
769bc1fd | 41 | select HAVE_OPROFILE |
9c57564e | 42 | select HAVE_PERF_EVENTS |
1b0ccb8a | 43 | select HANDLE_DOMAIN_IRQ |
999159a5 | 44 | select IRQ_DOMAIN |
cfdbc2e1 | 45 | select MODULES_USE_ELF_RELA |
999159a5 VG |
46 | select OF |
47 | select OF_EARLY_FLATTREE | |
20f1b79d | 48 | select PCI_SYSCALL if PCI |
82385732 | 49 | select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING |
cfdbc2e1 | 50 | |
eb277739 EP |
51 | config ARCH_HAS_CACHE_LINE_SIZE |
52 | def_bool y | |
53 | ||
0dafafc3 VG |
54 | config TRACE_IRQFLAGS_SUPPORT |
55 | def_bool y | |
56 | ||
57 | config LOCKDEP_SUPPORT | |
58 | def_bool y | |
59 | ||
cfdbc2e1 VG |
60 | config SCHED_OMIT_FRAME_POINTER |
61 | def_bool y | |
62 | ||
63 | config GENERIC_CSUM | |
64 | def_bool y | |
65 | ||
66 | config RWSEM_GENERIC_SPINLOCK | |
67 | def_bool y | |
68 | ||
26f9d5fd | 69 | config ARCH_DISCONTIGMEM_ENABLE |
d140b9bf | 70 | def_bool n |
26f9d5fd | 71 | |
cfdbc2e1 VG |
72 | config ARCH_FLATMEM_ENABLE |
73 | def_bool y | |
74 | ||
75 | config MMU | |
76 | def_bool y | |
77 | ||
ce816fa8 | 78 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
79 | def_bool y |
80 | ||
81 | config GENERIC_CALIBRATE_DELAY | |
82 | def_bool y | |
83 | ||
84 | config GENERIC_HWEIGHT | |
85 | def_bool y | |
86 | ||
44c8bb91 VG |
87 | config STACKTRACE_SUPPORT |
88 | def_bool y | |
89 | select STACKTRACE | |
90 | ||
fe6c1b86 VG |
91 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
92 | def_bool y | |
93 | depends on ARC_MMU_V4 | |
94 | ||
cfdbc2e1 VG |
95 | menu "ARC Architecture Configuration" |
96 | ||
93ad700d | 97 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 98 | |
072eb693 | 99 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 100 | source "arch/arc/plat-axs10x/Kconfig" |
cfdbc2e1 | 101 | #New platform adds here |
96665789 | 102 | source "arch/arc/plat-eznps/Kconfig" |
a518d637 | 103 | source "arch/arc/plat-hsdk/Kconfig" |
93ad700d | 104 | |
53d98958 | 105 | endmenu |
cfdbc2e1 | 106 | |
1f6ccfff VG |
107 | choice |
108 | prompt "ARC Instruction Set" | |
b7cc40c3 | 109 | default ISA_ARCV2 |
1f6ccfff VG |
110 | |
111 | config ISA_ARCOMPACT | |
112 | bool "ARCompact ISA" | |
fff7fb0b | 113 | select CPU_NO_EFFICIENT_FFS |
1f6ccfff VG |
114 | help |
115 | The original ARC ISA of ARC600/700 cores | |
116 | ||
65bfbcdf VG |
117 | config ISA_ARCV2 |
118 | bool "ARC ISA v2" | |
c4c9a040 | 119 | select ARC_TIMERS_64BIT |
65bfbcdf VG |
120 | help |
121 | ISA for the Next Generation ARC-HS cores | |
1f6ccfff VG |
122 | |
123 | endchoice | |
124 | ||
cfdbc2e1 VG |
125 | menu "ARC CPU Configuration" |
126 | ||
127 | choice | |
128 | prompt "ARC Core" | |
1f6ccfff VG |
129 | default ARC_CPU_770 if ISA_ARCOMPACT |
130 | default ARC_CPU_HS if ISA_ARCV2 | |
131 | ||
132 | if ISA_ARCOMPACT | |
cfdbc2e1 VG |
133 | |
134 | config ARC_CPU_750D | |
135 | bool "ARC750D" | |
14a0abfc | 136 | select ARC_CANT_LLSC |
cfdbc2e1 VG |
137 | help |
138 | Support for ARC750 core | |
139 | ||
140 | config ARC_CPU_770 | |
141 | bool "ARC770" | |
742f8af6 | 142 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
143 | help |
144 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
145 | This core has a bunch of cool new features: | |
146 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
7c2020c3 | 147 | Shared Address Spaces (for sharing TLB entries in MMU) |
cfdbc2e1 VG |
148 | -Caches: New Prog Model, Region Flush |
149 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
150 | ||
1f6ccfff VG |
151 | endif #ISA_ARCOMPACT |
152 | ||
153 | config ARC_CPU_HS | |
154 | bool "ARC-HS" | |
155 | depends on ISA_ARCV2 | |
156 | help | |
157 | Support for ARC HS38x Cores based on ARCv2 ISA | |
158 | The notable features are: | |
159 | - SMP configurations of upto 4 core with coherency | |
160 | - Optional L2 Cache and IO-Coherency | |
161 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
162 | auto stack switch, auto regfile save/restore) | |
163 | - MMUv4 (PIPT dcache, Huge Pages) | |
164 | - Instructions for | |
165 | * 64bit load/store: LDD, STD | |
166 | * Hardware assisted divide/remainder: DIV, REM | |
167 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
168 | * IRQ enable/disable: CLRI, SETI | |
169 | * pop count: FFS, FLS | |
170 | * SETcc, BMSKN, XBFU... | |
171 | ||
cfdbc2e1 VG |
172 | endchoice |
173 | ||
174 | config CPU_BIG_ENDIAN | |
175 | bool "Enable Big Endian Mode" | |
cfdbc2e1 VG |
176 | help |
177 | Build kernel for Big Endian Mode of ARC CPU | |
178 | ||
41195d23 | 179 | config SMP |
82fea5a1 | 180 | bool "Symmetric Multi-Processing" |
82fea5a1 | 181 | select ARC_MCIP if ISA_ARCV2 |
41195d23 | 182 | help |
82fea5a1 | 183 | This enables support for systems with more than one CPU. |
41195d23 VG |
184 | |
185 | if SMP | |
186 | ||
41195d23 | 187 | config NR_CPUS |
3aa4f80e NC |
188 | int "Maximum number of CPUs (2-4096)" |
189 | range 2 4096 | |
82fea5a1 VG |
190 | default "4" |
191 | ||
3971cdc2 VG |
192 | config ARC_SMP_HALT_ON_RESET |
193 | bool "Enable Halt-on-reset boot mode" | |
3971cdc2 VG |
194 | help |
195 | In SMP configuration cores can be configured as Halt-on-reset | |
196 | or they could all start at same time. For Halt-on-reset, non | |
197 | masters are parked until Master kicks them so they can start of | |
198 | at designated entry point. For other case, all jump to common | |
199 | entry point and spin wait for Master's signal. | |
200 | ||
82fea5a1 | 201 | endif #SMP |
41195d23 | 202 | |
3ce0fefc VG |
203 | config ARC_MCIP |
204 | bool "ARConnect Multicore IP (MCIP) Support " | |
205 | depends on ISA_ARCV2 | |
206 | default y if SMP | |
207 | help | |
208 | This IP block enables SMP in ARC-HS38 cores. | |
209 | It provides for cross-core interrupts, multi-core debug | |
210 | hardware semaphores, shared memory,.... | |
211 | ||
cfdbc2e1 VG |
212 | menuconfig ARC_CACHE |
213 | bool "Enable Cache Support" | |
214 | default y | |
215 | ||
216 | if ARC_CACHE | |
217 | ||
218 | config ARC_CACHE_LINE_SHIFT | |
219 | int "Cache Line Length (as power of 2)" | |
220 | range 5 7 | |
221 | default "6" | |
222 | help | |
223 | Starting with ARC700 4.9, Cache line length is configurable, | |
224 | This option specifies "N", with Line-len = 2 power N | |
225 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
226 | Linux only supports same line lengths for I and D caches. | |
227 | ||
228 | config ARC_HAS_ICACHE | |
229 | bool "Use Instruction Cache" | |
230 | default y | |
231 | ||
232 | config ARC_HAS_DCACHE | |
233 | bool "Use Data Cache" | |
234 | default y | |
235 | ||
236 | config ARC_CACHE_PAGES | |
237 | bool "Per Page Cache Control" | |
238 | default y | |
239 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
240 | help | |
241 | This can be used to over-ride the global I/D Cache Enable on a | |
242 | per-page basis (but only for pages accessed via MMU such as | |
243 | Kernel Virtual address or User Virtual Address) | |
244 | TLB entries have a per-page Cache Enable Bit. | |
245 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
246 | Global DISABLE + Per Page ENABLE won't work | |
247 | ||
4102b533 VG |
248 | config ARC_CACHE_VIPT_ALIASING |
249 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 250 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 | 251 | |
cfdbc2e1 VG |
252 | endif #ARC_CACHE |
253 | ||
8b5850f8 VG |
254 | config ARC_HAS_ICCM |
255 | bool "Use ICCM" | |
256 | help | |
257 | Single Cycle RAMS to store Fast Path Code | |
8b5850f8 VG |
258 | |
259 | config ARC_ICCM_SZ | |
260 | int "ICCM Size in KB" | |
261 | default "64" | |
262 | depends on ARC_HAS_ICCM | |
263 | ||
264 | config ARC_HAS_DCCM | |
265 | bool "Use DCCM" | |
266 | help | |
267 | Single Cycle RAMS to store Fast Path Data | |
8b5850f8 VG |
268 | |
269 | config ARC_DCCM_SZ | |
270 | int "DCCM Size in KB" | |
271 | default "64" | |
272 | depends on ARC_HAS_DCCM | |
273 | ||
274 | config ARC_DCCM_BASE | |
275 | hex "DCCM map address" | |
276 | default "0xA0000000" | |
277 | depends on ARC_HAS_DCCM | |
278 | ||
cfdbc2e1 | 279 | choice |
1f6ccfff | 280 | prompt "MMU Version" |
cfdbc2e1 VG |
281 | default ARC_MMU_V3 if ARC_CPU_770 |
282 | default ARC_MMU_V2 if ARC_CPU_750D | |
d7a512bf | 283 | default ARC_MMU_V4 if ARC_CPU_HS |
cfdbc2e1 | 284 | |
c583ee4f VG |
285 | if ISA_ARCOMPACT |
286 | ||
cfdbc2e1 VG |
287 | config ARC_MMU_V1 |
288 | bool "MMU v1" | |
289 | help | |
290 | Orig ARC700 MMU | |
291 | ||
292 | config ARC_MMU_V2 | |
293 | bool "MMU v2" | |
294 | help | |
83fc61a5 | 295 | Fixed the deficiency of v1 - possible thrashing in memcpy scenario |
cfdbc2e1 VG |
296 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. |
297 | ||
298 | config ARC_MMU_V3 | |
299 | bool "MMU v3" | |
300 | depends on ARC_CPU_770 | |
301 | help | |
302 | Introduced with ARC700 4.10: New Features | |
303 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
304 | Shared Address Spaces (SASID) | |
305 | ||
c583ee4f VG |
306 | endif |
307 | ||
d7a512bf VG |
308 | config ARC_MMU_V4 |
309 | bool "MMU v4" | |
310 | depends on ISA_ARCV2 | |
311 | ||
cfdbc2e1 VG |
312 | endchoice |
313 | ||
314 | ||
315 | choice | |
316 | prompt "MMU Page Size" | |
317 | default ARC_PAGE_SIZE_8K | |
318 | ||
319 | config ARC_PAGE_SIZE_8K | |
320 | bool "8KB" | |
321 | help | |
322 | Choose between 8k vs 16k | |
323 | ||
324 | config ARC_PAGE_SIZE_16K | |
325 | bool "16KB" | |
450ed0db | 326 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
327 | |
328 | config ARC_PAGE_SIZE_4K | |
329 | bool "4KB" | |
450ed0db | 330 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
331 | |
332 | endchoice | |
333 | ||
37eda9df VG |
334 | choice |
335 | prompt "MMU Super Page Size" | |
336 | depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE | |
337 | default ARC_HUGEPAGE_2M | |
338 | ||
339 | config ARC_HUGEPAGE_2M | |
340 | bool "2MB" | |
341 | ||
342 | config ARC_HUGEPAGE_16M | |
343 | bool "16MB" | |
344 | ||
345 | endchoice | |
346 | ||
26f9d5fd VG |
347 | config NODES_SHIFT |
348 | int "Maximum NUMA Nodes (as a power of 2)" | |
3528f84f NC |
349 | default "0" if !DISCONTIGMEM |
350 | default "1" if DISCONTIGMEM | |
26f9d5fd VG |
351 | depends on NEED_MULTIPLE_NODES |
352 | ---help--- | |
353 | Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory | |
354 | zones. | |
355 | ||
1f6ccfff VG |
356 | if ISA_ARCOMPACT |
357 | ||
4788a594 | 358 | config ARC_COMPACT_IRQ_LEVELS |
60f2b4b8 | 359 | bool "Setup Timer IRQ as high Priority" |
41195d23 | 360 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
60f2b4b8 | 361 | depends on !SMP |
4788a594 | 362 | |
cfdbc2e1 VG |
363 | config ARC_FPU_SAVE_RESTORE |
364 | bool "Enable FPU state persistence across context switch" | |
cfdbc2e1 | 365 | help |
83fc61a5 | 366 | Double Precision Floating Point unit had dedicated regs which |
cfdbc2e1 VG |
367 | need to be saved/restored across context-switch. |
368 | Note that ARC FPU is overly simplistic, unlike say x86, which has | |
369 | hardware pieces to allow software to conditionally save/restore, | |
370 | based on actual usage of FPU by a task. Thus our implemn does | |
371 | this for all tasks in system. | |
372 | ||
1f6ccfff VG |
373 | endif #ISA_ARCOMPACT |
374 | ||
fbf8e13d VG |
375 | config ARC_CANT_LLSC |
376 | def_bool n | |
377 | ||
cfdbc2e1 VG |
378 | config ARC_HAS_LLSC |
379 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
380 | default y | |
14a0abfc | 381 | depends on !ARC_CANT_LLSC |
cfdbc2e1 VG |
382 | |
383 | config ARC_HAS_SWAPE | |
384 | bool "Insn: SWAPE (endian-swap)" | |
385 | default y | |
cfdbc2e1 | 386 | |
1f6ccfff VG |
387 | if ISA_ARCV2 |
388 | ||
389 | config ARC_HAS_LL64 | |
390 | bool "Insn: 64bit LDD/STD" | |
391 | help | |
392 | Enable gcc to generate 64-bit load/store instructions | |
393 | ISA mandates even/odd registers to allow encoding of two | |
394 | dest operands with 2 possible source operands. | |
395 | default y | |
396 | ||
d05a76ab AB |
397 | config ARC_HAS_DIV_REM |
398 | bool "Insn: div, divu, rem, remu" | |
399 | default y | |
400 | ||
3d5e8012 VG |
401 | config ARC_HAS_ACCL_REGS |
402 | bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" | |
af1fc5ba | 403 | default y |
3d5e8012 VG |
404 | help |
405 | Depending on the configuration, CPU can contain accumulator reg-pair | |
406 | (also referred to as r58:r59). These can also be used by gcc as GPR so | |
407 | kernel needs to save/restore per process | |
408 | ||
e494239a VG |
409 | config ARC_IRQ_NO_AUTOSAVE |
410 | bool "Disable hardware autosave regfile on interrupts" | |
411 | default n | |
412 | help | |
413 | On HS cores, taken interrupt auto saves the regfile on stack. | |
414 | This is programmable and can be optionally disabled in which case | |
415 | software INTERRUPT_PROLOGUE/EPILGUE do the needed work | |
416 | ||
1f6ccfff VG |
417 | endif # ISA_ARCV2 |
418 | ||
cfdbc2e1 VG |
419 | endmenu # "ARC CPU Configuration" |
420 | ||
cfdbc2e1 | 421 | config LINUX_LINK_BASE |
9ed68785 | 422 | hex "Kernel link address" |
cfdbc2e1 VG |
423 | default "0x80000000" |
424 | help | |
425 | ARC700 divides the 32 bit phy address space into two equal halves | |
426 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
427 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
428 | Typically Linux kernel is linked at the start of untransalted addr, | |
429 | hence the default value of 0x8zs. | |
430 | However some customers have peripherals mapped at this addr, so | |
431 | Linux needs to be scooted a bit. | |
432 | If you don't know what the above means, leave this setting alone. | |
ff1c0b6a | 433 | This needs to match memory start address specified in Device Tree |
cfdbc2e1 | 434 | |
9ed68785 EP |
435 | config LINUX_RAM_BASE |
436 | hex "RAM base address" | |
437 | default LINUX_LINK_BASE | |
438 | help | |
439 | By default Linux is linked at base of RAM. However in some special | |
440 | cases (such as HSDK), Linux can't be linked at start of DDR, hence | |
441 | this option. | |
442 | ||
45890f6d VG |
443 | config HIGHMEM |
444 | bool "High Memory Support" | |
d140b9bf | 445 | select ARCH_DISCONTIGMEM_ENABLE |
45890f6d VG |
446 | help |
447 | With ARC 2G:2G address split, only upper 2G is directly addressable by | |
448 | kernel. Enable this to potentially allow access to rest of 2G and PAE | |
449 | in future | |
450 | ||
5a364c2a VG |
451 | config ARC_HAS_PAE40 |
452 | bool "Support for the 40-bit Physical Address Extension" | |
5a364c2a | 453 | depends on ISA_ARCV2 |
cf4100d1 | 454 | select HIGHMEM |
d4a451d5 | 455 | select PHYS_ADDR_T_64BIT |
5a364c2a VG |
456 | help |
457 | Enable access to physical memory beyond 4G, only supported on | |
458 | ARC cores with 40 bit Physical Addressing support | |
459 | ||
15ca68a9 | 460 | config ARC_KVADDR_SIZE |
83fc61a5 | 461 | int "Kernel Virtual Address Space size (MB)" |
15ca68a9 NC |
462 | range 0 512 |
463 | default "256" | |
464 | help | |
465 | The kernel address space is carved out of 256MB of translated address | |
466 | space for catering to vmalloc, modules, pkmap, fixmap. This however may | |
467 | not suffice vmalloc requirements of a 4K CPU EZChip system. So allow | |
468 | this to be stretched to 512 MB (by extending into the reserved | |
469 | kernel-user gutter) | |
470 | ||
080c3747 VG |
471 | config ARC_CURR_IN_REG |
472 | bool "Dedicate Register r25 for current_task pointer" | |
473 | default y | |
474 | help | |
475 | This reserved Register R25 to point to Current Task in | |
476 | kernel mode. This saves memory access for each such access | |
477 | ||
2e651ea1 | 478 | |
1736a56f | 479 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 480 | bool "Emulate unaligned memory access (userspace only)" |
2e651ea1 VG |
481 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
482 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 483 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
484 | help |
485 | This enables misaligned 16 & 32 bit memory access from user space. | |
486 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
487 | potential bugs in code | |
488 | ||
cfdbc2e1 VG |
489 | config HZ |
490 | int "Timer Frequency" | |
491 | default 100 | |
492 | ||
cbe056f7 VG |
493 | config ARC_METAWARE_HLINK |
494 | bool "Support for Metaware debugger assisted Host access" | |
cbe056f7 VG |
495 | help |
496 | This options allows a Linux userland apps to directly access | |
497 | host file system (open/creat/read/write etc) with help from | |
498 | Metaware Debugger. This can come in handy for Linux-host communication | |
499 | when there is no real usable peripheral such as EMAC. | |
500 | ||
cfdbc2e1 VG |
501 | menuconfig ARC_DBG |
502 | bool "ARC debugging" | |
503 | default y | |
504 | ||
aa6083ed VG |
505 | if ARC_DBG |
506 | ||
854a0d95 VG |
507 | config ARC_DW2_UNWIND |
508 | bool "Enable DWARF specific kernel stack unwind" | |
854a0d95 VG |
509 | default y |
510 | select KALLSYMS | |
511 | help | |
512 | Compiles the kernel with DWARF unwind information and can be used | |
513 | to get stack backtraces. | |
514 | ||
515 | If you say Y here the resulting kernel image will be slightly larger | |
516 | but not slower, and it will give very useful debugging information. | |
517 | If you don't debug the kernel, you can say N, but we may not be able | |
518 | to solve problems without frame unwind information | |
519 | ||
cfdbc2e1 VG |
520 | config ARC_DBG_TLB_PARANOIA |
521 | bool "Paranoia Checks in Low Level TLB Handlers" | |
cfdbc2e1 | 522 | |
aa6083ed VG |
523 | endif |
524 | ||
999159a5 VG |
525 | config ARC_BUILTIN_DTB_NAME |
526 | string "Built in DTB" | |
527 | help | |
528 | Set the name of the DTB to embed in the vmlinux binary | |
529 | Leaving it blank selects the minimal "skeleton" dtb | |
530 | ||
cfdbc2e1 VG |
531 | endmenu # "ARC Architecture Configuration" |
532 | ||
37eda9df VG |
533 | config FORCE_MAX_ZONEORDER |
534 | int "Maximum zone order" | |
535 | default "12" if ARC_HUGEPAGE_16M | |
536 | default "11" | |
537 | ||
996bad6c | 538 | source "kernel/power/Kconfig" |