Commit | Line | Data |
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d2912cb1 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
cfdbc2e1 VG |
2 | # |
3 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
4 | # | |
cfdbc2e1 VG |
5 | |
6 | config ARC | |
7 | def_bool y | |
c4c9a040 | 8 | select ARC_TIMERS |
c2280be8 | 9 | select ARCH_HAS_CACHE_LINE_SIZE |
399145f9 | 10 | select ARCH_HAS_DEBUG_VM_PGTABLE |
f73c9045 | 11 | select ARCH_HAS_DMA_PREP_COHERENT |
c27d0e90 | 12 | select ARCH_HAS_PTE_SPECIAL |
347cb6af | 13 | select ARCH_HAS_SETUP_DMA_OPS |
6c3e71dd CH |
14 | select ARCH_HAS_SYNC_DMA_FOR_CPU |
15 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE | |
2a440168 | 16 | select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
942fa985 | 17 | select ARCH_32BIT_OFF_T |
10916706 | 18 | select BUILDTIME_TABLE_SORT |
4adeefe1 | 19 | select CLONE_BACKWARDS |
69fbd098 | 20 | select COMMON_CLK |
f73c9045 | 21 | select DMA_DIRECT_REMAP |
ce636527 | 22 | select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) |
cfdbc2e1 VG |
23 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP |
24 | select GENERIC_IRQ_SHOW | |
c1678ffc | 25 | select GENERIC_PCI_IOMAP |
cfdbc2e1 | 26 | select GENERIC_PENDING_IRQ if SMP |
bf287607 | 27 | select GENERIC_SCHED_CLOCK |
cfdbc2e1 | 28 | select GENERIC_SMP_IDLE_THREAD |
f46121bd | 29 | select HAVE_ARCH_KGDB |
547f1125 | 30 | select HAVE_ARCH_TRACEHOOK |
e8003bf6 | 31 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4 |
c27d0e90 | 32 | select HAVE_DEBUG_STACKOVERFLOW |
9fbea0b7 | 33 | select HAVE_DEBUG_KMEMLEAK |
4368902b | 34 | select HAVE_IOREMAP_PROT |
c27d0e90 VG |
35 | select HAVE_KERNEL_GZIP |
36 | select HAVE_KERNEL_LZMA | |
4d86dfbb VG |
37 | select HAVE_KPROBES |
38 | select HAVE_KRETPROBES | |
b3bbf6a7 | 39 | select HAVE_REGS_AND_STACK_ACCESS_API |
eb1357d9 | 40 | select HAVE_MOD_ARCH_SPECIFIC |
9c57564e | 41 | select HAVE_PERF_EVENTS |
fb0b5490 | 42 | select HAVE_SYSCALL_TRACEPOINTS |
999159a5 | 43 | select IRQ_DOMAIN |
cfdbc2e1 | 44 | select MODULES_USE_ELF_RELA |
999159a5 VG |
45 | select OF |
46 | select OF_EARLY_FLATTREE | |
20f1b79d | 47 | select PCI_SYSCALL if PCI |
82385732 | 48 | select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING |
f091d5a4 | 49 | select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 |
4aae683f | 50 | select TRACE_IRQFLAGS_SUPPORT |
0dafafc3 VG |
51 | |
52 | config LOCKDEP_SUPPORT | |
53 | def_bool y | |
54 | ||
cfdbc2e1 VG |
55 | config SCHED_OMIT_FRAME_POINTER |
56 | def_bool y | |
57 | ||
58 | config GENERIC_CSUM | |
59 | def_bool y | |
60 | ||
cfdbc2e1 VG |
61 | config ARCH_FLATMEM_ENABLE |
62 | def_bool y | |
63 | ||
64 | config MMU | |
65 | def_bool y | |
66 | ||
ce816fa8 | 67 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
68 | def_bool y |
69 | ||
70 | config GENERIC_CALIBRATE_DELAY | |
71 | def_bool y | |
72 | ||
73 | config GENERIC_HWEIGHT | |
74 | def_bool y | |
75 | ||
44c8bb91 VG |
76 | config STACKTRACE_SUPPORT |
77 | def_bool y | |
78 | select STACKTRACE | |
79 | ||
cfdbc2e1 VG |
80 | menu "ARC Architecture Configuration" |
81 | ||
93ad700d | 82 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 83 | |
072eb693 | 84 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 85 | source "arch/arc/plat-axs10x/Kconfig" |
a518d637 | 86 | source "arch/arc/plat-hsdk/Kconfig" |
93ad700d | 87 | |
53d98958 | 88 | endmenu |
cfdbc2e1 | 89 | |
1f6ccfff VG |
90 | choice |
91 | prompt "ARC Instruction Set" | |
b7cc40c3 | 92 | default ISA_ARCV2 |
1f6ccfff VG |
93 | |
94 | config ISA_ARCOMPACT | |
95 | bool "ARCompact ISA" | |
fff7fb0b | 96 | select CPU_NO_EFFICIENT_FFS |
1f6ccfff VG |
97 | help |
98 | The original ARC ISA of ARC600/700 cores | |
99 | ||
65bfbcdf VG |
100 | config ISA_ARCV2 |
101 | bool "ARC ISA v2" | |
c4c9a040 | 102 | select ARC_TIMERS_64BIT |
65bfbcdf VG |
103 | help |
104 | ISA for the Next Generation ARC-HS cores | |
1f6ccfff VG |
105 | |
106 | endchoice | |
107 | ||
cfdbc2e1 VG |
108 | menu "ARC CPU Configuration" |
109 | ||
110 | choice | |
111 | prompt "ARC Core" | |
1f6ccfff VG |
112 | default ARC_CPU_770 if ISA_ARCOMPACT |
113 | default ARC_CPU_HS if ISA_ARCV2 | |
114 | ||
cfdbc2e1 VG |
115 | config ARC_CPU_770 |
116 | bool "ARC770" | |
767a697e | 117 | depends on ISA_ARCOMPACT |
742f8af6 | 118 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
119 | help |
120 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
121 | This core has a bunch of cool new features: | |
122 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
9a18b5a4 | 123 | Shared Address Spaces (for sharing TLB entries in MMU) |
cfdbc2e1 VG |
124 | -Caches: New Prog Model, Region Flush |
125 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
126 | ||
1f6ccfff VG |
127 | config ARC_CPU_HS |
128 | bool "ARC-HS" | |
129 | depends on ISA_ARCV2 | |
130 | help | |
131 | Support for ARC HS38x Cores based on ARCv2 ISA | |
132 | The notable features are: | |
a5760db2 | 133 | - SMP configurations of up to 4 cores with coherency |
1f6ccfff VG |
134 | - Optional L2 Cache and IO-Coherency |
135 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
136 | auto stack switch, auto regfile save/restore) | |
137 | - MMUv4 (PIPT dcache, Huge Pages) | |
138 | - Instructions for | |
139 | * 64bit load/store: LDD, STD | |
140 | * Hardware assisted divide/remainder: DIV, REM | |
141 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
142 | * IRQ enable/disable: CLRI, SETI | |
143 | * pop count: FFS, FLS | |
144 | * SETcc, BMSKN, XBFU... | |
145 | ||
cfdbc2e1 VG |
146 | endchoice |
147 | ||
0bdd6e74 EP |
148 | config ARC_TUNE_MCPU |
149 | string "Override default -mcpu compiler flag" | |
150 | default "" | |
151 | help | |
152 | Override default -mcpu=xxx compiler flag (which is set depending on | |
153 | the ISA version) with the specified value. | |
154 | NOTE: If specified flag isn't supported by current compiler the | |
155 | ISA default value will be used as a fallback. | |
156 | ||
cfdbc2e1 VG |
157 | config CPU_BIG_ENDIAN |
158 | bool "Enable Big Endian Mode" | |
cfdbc2e1 VG |
159 | help |
160 | Build kernel for Big Endian Mode of ARC CPU | |
161 | ||
41195d23 | 162 | config SMP |
82fea5a1 | 163 | bool "Symmetric Multi-Processing" |
82fea5a1 | 164 | select ARC_MCIP if ISA_ARCV2 |
41195d23 | 165 | help |
82fea5a1 | 166 | This enables support for systems with more than one CPU. |
41195d23 VG |
167 | |
168 | if SMP | |
169 | ||
41195d23 | 170 | config NR_CPUS |
3aa4f80e NC |
171 | int "Maximum number of CPUs (2-4096)" |
172 | range 2 4096 | |
82fea5a1 VG |
173 | default "4" |
174 | ||
3971cdc2 VG |
175 | config ARC_SMP_HALT_ON_RESET |
176 | bool "Enable Halt-on-reset boot mode" | |
3971cdc2 VG |
177 | help |
178 | In SMP configuration cores can be configured as Halt-on-reset | |
179 | or they could all start at same time. For Halt-on-reset, non | |
a5760db2 | 180 | masters are parked until Master kicks them so they can start off |
3971cdc2 VG |
181 | at designated entry point. For other case, all jump to common |
182 | entry point and spin wait for Master's signal. | |
183 | ||
9a18b5a4 | 184 | endif #SMP |
41195d23 | 185 | |
3ce0fefc VG |
186 | config ARC_MCIP |
187 | bool "ARConnect Multicore IP (MCIP) Support " | |
188 | depends on ISA_ARCV2 | |
189 | default y if SMP | |
190 | help | |
191 | This IP block enables SMP in ARC-HS38 cores. | |
192 | It provides for cross-core interrupts, multi-core debug | |
193 | hardware semaphores, shared memory,.... | |
194 | ||
cfdbc2e1 VG |
195 | menuconfig ARC_CACHE |
196 | bool "Enable Cache Support" | |
197 | default y | |
198 | ||
199 | if ARC_CACHE | |
200 | ||
201 | config ARC_CACHE_LINE_SHIFT | |
202 | int "Cache Line Length (as power of 2)" | |
203 | range 5 7 | |
204 | default "6" | |
205 | help | |
206 | Starting with ARC700 4.9, Cache line length is configurable, | |
207 | This option specifies "N", with Line-len = 2 power N | |
208 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
209 | Linux only supports same line lengths for I and D caches. | |
210 | ||
211 | config ARC_HAS_ICACHE | |
212 | bool "Use Instruction Cache" | |
213 | default y | |
214 | ||
215 | config ARC_HAS_DCACHE | |
216 | bool "Use Data Cache" | |
217 | default y | |
218 | ||
219 | config ARC_CACHE_PAGES | |
220 | bool "Per Page Cache Control" | |
221 | default y | |
222 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
223 | help | |
224 | This can be used to over-ride the global I/D Cache Enable on a | |
225 | per-page basis (but only for pages accessed via MMU such as | |
226 | Kernel Virtual address or User Virtual Address) | |
227 | TLB entries have a per-page Cache Enable Bit. | |
228 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
229 | Global DISABLE + Per Page ENABLE won't work | |
230 | ||
4102b533 VG |
231 | config ARC_CACHE_VIPT_ALIASING |
232 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 233 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 | 234 | |
9a18b5a4 | 235 | endif #ARC_CACHE |
cfdbc2e1 | 236 | |
8b5850f8 VG |
237 | config ARC_HAS_ICCM |
238 | bool "Use ICCM" | |
239 | help | |
240 | Single Cycle RAMS to store Fast Path Code | |
8b5850f8 VG |
241 | |
242 | config ARC_ICCM_SZ | |
243 | int "ICCM Size in KB" | |
244 | default "64" | |
245 | depends on ARC_HAS_ICCM | |
246 | ||
247 | config ARC_HAS_DCCM | |
248 | bool "Use DCCM" | |
249 | help | |
250 | Single Cycle RAMS to store Fast Path Data | |
8b5850f8 VG |
251 | |
252 | config ARC_DCCM_SZ | |
253 | int "DCCM Size in KB" | |
254 | default "64" | |
255 | depends on ARC_HAS_DCCM | |
256 | ||
257 | config ARC_DCCM_BASE | |
258 | hex "DCCM map address" | |
259 | default "0xA0000000" | |
260 | depends on ARC_HAS_DCCM | |
261 | ||
cfdbc2e1 | 262 | choice |
1f6ccfff | 263 | prompt "MMU Version" |
288ff7de VG |
264 | default ARC_MMU_V3 if ISA_ARCOMPACT |
265 | default ARC_MMU_V4 if ISA_ARCV2 | |
cfdbc2e1 VG |
266 | |
267 | config ARC_MMU_V3 | |
268 | bool "MMU v3" | |
288ff7de | 269 | depends on ISA_ARCOMPACT |
cfdbc2e1 VG |
270 | help |
271 | Introduced with ARC700 4.10: New Features | |
272 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
273 | Shared Address Spaces (SASID) | |
274 | ||
d7a512bf VG |
275 | config ARC_MMU_V4 |
276 | bool "MMU v4" | |
277 | depends on ISA_ARCV2 | |
278 | ||
cfdbc2e1 VG |
279 | endchoice |
280 | ||
281 | ||
282 | choice | |
283 | prompt "MMU Page Size" | |
284 | default ARC_PAGE_SIZE_8K | |
285 | ||
286 | config ARC_PAGE_SIZE_8K | |
287 | bool "8KB" | |
288 | help | |
289 | Choose between 8k vs 16k | |
290 | ||
291 | config ARC_PAGE_SIZE_16K | |
292 | bool "16KB" | |
cfdbc2e1 VG |
293 | |
294 | config ARC_PAGE_SIZE_4K | |
295 | bool "4KB" | |
450ed0db | 296 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
297 | |
298 | endchoice | |
299 | ||
37eda9df VG |
300 | choice |
301 | prompt "MMU Super Page Size" | |
302 | depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE | |
303 | default ARC_HUGEPAGE_2M | |
304 | ||
305 | config ARC_HUGEPAGE_2M | |
306 | bool "2MB" | |
307 | ||
308 | config ARC_HUGEPAGE_16M | |
309 | bool "16MB" | |
310 | ||
311 | endchoice | |
312 | ||
2dde02ab VG |
313 | config PGTABLE_LEVELS |
314 | int "Number of Page table levels" | |
315 | default 2 | |
316 | ||
4788a594 | 317 | config ARC_COMPACT_IRQ_LEVELS |
f45ba2bd | 318 | depends on ISA_ARCOMPACT |
60f2b4b8 | 319 | bool "Setup Timer IRQ as high Priority" |
41195d23 | 320 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
60f2b4b8 | 321 | depends on !SMP |
4788a594 | 322 | |
cfdbc2e1 VG |
323 | config ARC_FPU_SAVE_RESTORE |
324 | bool "Enable FPU state persistence across context switch" | |
cfdbc2e1 | 325 | help |
f45ba2bd VG |
326 | ARCompact FPU has internal registers to assist with Double precision |
327 | Floating Point operations. There are control and stauts registers | |
328 | for floating point exceptions and rounding modes. These are | |
329 | preserved across task context switch when enabled. | |
1f6ccfff | 330 | |
fbf8e13d VG |
331 | config ARC_CANT_LLSC |
332 | def_bool n | |
333 | ||
cfdbc2e1 VG |
334 | config ARC_HAS_LLSC |
335 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
336 | default y | |
14a0abfc | 337 | depends on !ARC_CANT_LLSC |
cfdbc2e1 VG |
338 | |
339 | config ARC_HAS_SWAPE | |
340 | bool "Insn: SWAPE (endian-swap)" | |
341 | default y | |
cfdbc2e1 | 342 | |
1f6ccfff VG |
343 | if ISA_ARCV2 |
344 | ||
76551468 EP |
345 | config ARC_USE_UNALIGNED_MEM_ACCESS |
346 | bool "Enable unaligned access in HW" | |
347 | default y | |
348 | select HAVE_EFFICIENT_UNALIGNED_ACCESS | |
349 | help | |
350 | The ARC HS architecture supports unaligned memory access | |
351 | which is disabled by default. Enable unaligned access in | |
352 | hardware and use software to use it | |
353 | ||
1f6ccfff VG |
354 | config ARC_HAS_LL64 |
355 | bool "Insn: 64bit LDD/STD" | |
356 | help | |
357 | Enable gcc to generate 64-bit load/store instructions | |
358 | ISA mandates even/odd registers to allow encoding of two | |
359 | dest operands with 2 possible source operands. | |
360 | default y | |
361 | ||
d05a76ab AB |
362 | config ARC_HAS_DIV_REM |
363 | bool "Insn: div, divu, rem, remu" | |
364 | default y | |
365 | ||
3d5e8012 | 366 | config ARC_HAS_ACCL_REGS |
4827d0cf | 367 | bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" |
af1fc5ba | 368 | default y |
3d5e8012 VG |
369 | help |
370 | Depending on the configuration, CPU can contain accumulator reg-pair | |
371 | (also referred to as r58:r59). These can also be used by gcc as GPR so | |
372 | kernel needs to save/restore per process | |
373 | ||
4827d0cf EP |
374 | config ARC_DSP_HANDLED |
375 | def_bool n | |
376 | ||
7321e2ea EP |
377 | config ARC_DSP_SAVE_RESTORE_REGS |
378 | def_bool n | |
379 | ||
4827d0cf EP |
380 | choice |
381 | prompt "DSP support" | |
382 | default ARC_DSP_NONE | |
383 | help | |
384 | Depending on the configuration, CPU can contain DSP registers | |
385 | (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). | |
81e82fa5 | 386 | Below are options describing how to handle these registers in |
4827d0cf EP |
387 | interrupt entry / exit and in context switch. |
388 | ||
389 | config ARC_DSP_NONE | |
390 | bool "No DSP extension presence in HW" | |
391 | help | |
392 | No DSP extension presence in HW | |
393 | ||
394 | config ARC_DSP_KERNEL | |
395 | bool "DSP extension in HW, no support for userspace" | |
396 | select ARC_HAS_ACCL_REGS | |
397 | select ARC_DSP_HANDLED | |
398 | help | |
399 | DSP extension presence in HW, no support for DSP-enabled userspace | |
400 | applications. We don't save / restore DSP registers and only do | |
401 | some minimal preparations so userspace won't be able to break kernel | |
7321e2ea EP |
402 | |
403 | config ARC_DSP_USERSPACE | |
404 | bool "Support DSP for userspace apps" | |
405 | select ARC_HAS_ACCL_REGS | |
406 | select ARC_DSP_HANDLED | |
407 | select ARC_DSP_SAVE_RESTORE_REGS | |
408 | help | |
409 | DSP extension presence in HW, support save / restore DSP registers to | |
410 | run DSP-enabled userspace applications | |
f09d3174 EP |
411 | |
412 | config ARC_DSP_AGU_USERSPACE | |
413 | bool "Support DSP with AGU for userspace apps" | |
414 | select ARC_HAS_ACCL_REGS | |
415 | select ARC_DSP_HANDLED | |
416 | select ARC_DSP_SAVE_RESTORE_REGS | |
417 | help | |
418 | DSP and AGU extensions presence in HW, support save / restore DSP | |
419 | and AGU registers to run DSP-enabled userspace applications | |
4827d0cf EP |
420 | endchoice |
421 | ||
e494239a VG |
422 | config ARC_IRQ_NO_AUTOSAVE |
423 | bool "Disable hardware autosave regfile on interrupts" | |
424 | default n | |
425 | help | |
426 | On HS cores, taken interrupt auto saves the regfile on stack. | |
427 | This is programmable and can be optionally disabled in which case | |
428 | software INTERRUPT_PROLOGUE/EPILGUE do the needed work | |
429 | ||
10011f7d EP |
430 | config ARC_LPB_DISABLE |
431 | bool "Disable loop buffer (LPB)" | |
432 | help | |
433 | On HS cores, loop buffer (LPB) is programmable in runtime and can | |
434 | be optionally disabled. | |
435 | ||
9a18b5a4 | 436 | endif # ISA_ARCV2 |
1f6ccfff | 437 | |
cfdbc2e1 VG |
438 | endmenu # "ARC CPU Configuration" |
439 | ||
cfdbc2e1 | 440 | config LINUX_LINK_BASE |
9ed68785 | 441 | hex "Kernel link address" |
cfdbc2e1 VG |
442 | default "0x80000000" |
443 | help | |
444 | ARC700 divides the 32 bit phy address space into two equal halves | |
445 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
446 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
447 | Typically Linux kernel is linked at the start of untransalted addr, | |
448 | hence the default value of 0x8zs. | |
449 | However some customers have peripherals mapped at this addr, so | |
450 | Linux needs to be scooted a bit. | |
451 | If you don't know what the above means, leave this setting alone. | |
ff1c0b6a | 452 | This needs to match memory start address specified in Device Tree |
cfdbc2e1 | 453 | |
9ed68785 EP |
454 | config LINUX_RAM_BASE |
455 | hex "RAM base address" | |
456 | default LINUX_LINK_BASE | |
457 | help | |
458 | By default Linux is linked at base of RAM. However in some special | |
459 | cases (such as HSDK), Linux can't be linked at start of DDR, hence | |
460 | this option. | |
461 | ||
45890f6d VG |
462 | config HIGHMEM |
463 | bool "High Memory Support" | |
050b2da2 | 464 | select HAVE_ARCH_PFN_VALID |
39cac191 | 465 | select KMAP_LOCAL |
45890f6d VG |
466 | help |
467 | With ARC 2G:2G address split, only upper 2G is directly addressable by | |
468 | kernel. Enable this to potentially allow access to rest of 2G and PAE | |
469 | in future | |
470 | ||
5a364c2a VG |
471 | config ARC_HAS_PAE40 |
472 | bool "Support for the 40-bit Physical Address Extension" | |
5a364c2a | 473 | depends on ISA_ARCV2 |
cf4100d1 | 474 | select HIGHMEM |
d4a451d5 | 475 | select PHYS_ADDR_T_64BIT |
5a364c2a VG |
476 | help |
477 | Enable access to physical memory beyond 4G, only supported on | |
478 | ARC cores with 40 bit Physical Addressing support | |
479 | ||
15ca68a9 | 480 | config ARC_KVADDR_SIZE |
83fc61a5 | 481 | int "Kernel Virtual Address Space size (MB)" |
15ca68a9 NC |
482 | range 0 512 |
483 | default "256" | |
484 | help | |
485 | The kernel address space is carved out of 256MB of translated address | |
486 | space for catering to vmalloc, modules, pkmap, fixmap. This however may | |
487 | not suffice vmalloc requirements of a 4K CPU EZChip system. So allow | |
488 | this to be stretched to 512 MB (by extending into the reserved | |
489 | kernel-user gutter) | |
490 | ||
080c3747 VG |
491 | config ARC_CURR_IN_REG |
492 | bool "Dedicate Register r25 for current_task pointer" | |
493 | default y | |
494 | help | |
495 | This reserved Register R25 to point to Current Task in | |
496 | kernel mode. This saves memory access for each such access | |
497 | ||
2e651ea1 | 498 | |
1736a56f | 499 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 500 | bool "Emulate unaligned memory access (userspace only)" |
2e651ea1 VG |
501 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
502 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 503 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
504 | help |
505 | This enables misaligned 16 & 32 bit memory access from user space. | |
506 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
507 | potential bugs in code | |
508 | ||
cfdbc2e1 VG |
509 | config HZ |
510 | int "Timer Frequency" | |
511 | default 100 | |
512 | ||
cbe056f7 VG |
513 | config ARC_METAWARE_HLINK |
514 | bool "Support for Metaware debugger assisted Host access" | |
cbe056f7 VG |
515 | help |
516 | This options allows a Linux userland apps to directly access | |
517 | host file system (open/creat/read/write etc) with help from | |
518 | Metaware Debugger. This can come in handy for Linux-host communication | |
519 | when there is no real usable peripheral such as EMAC. | |
520 | ||
cfdbc2e1 VG |
521 | menuconfig ARC_DBG |
522 | bool "ARC debugging" | |
523 | default y | |
524 | ||
aa6083ed VG |
525 | if ARC_DBG |
526 | ||
854a0d95 VG |
527 | config ARC_DW2_UNWIND |
528 | bool "Enable DWARF specific kernel stack unwind" | |
854a0d95 VG |
529 | default y |
530 | select KALLSYMS | |
531 | help | |
532 | Compiles the kernel with DWARF unwind information and can be used | |
533 | to get stack backtraces. | |
534 | ||
535 | If you say Y here the resulting kernel image will be slightly larger | |
536 | but not slower, and it will give very useful debugging information. | |
537 | If you don't debug the kernel, you can say N, but we may not be able | |
538 | to solve problems without frame unwind information | |
539 | ||
f091d5a4 EP |
540 | config ARC_DBG_JUMP_LABEL |
541 | bool "Paranoid checks in Static Keys (jump labels) code" | |
542 | depends on JUMP_LABEL | |
543 | default y if STATIC_KEYS_SELFTEST | |
544 | help | |
545 | Enable paranoid checks and self-test of both ARC-specific and generic | |
546 | part of static keys (jump labels) related code. | |
aa6083ed VG |
547 | endif |
548 | ||
999159a5 VG |
549 | config ARC_BUILTIN_DTB_NAME |
550 | string "Built in DTB" | |
551 | help | |
552 | Set the name of the DTB to embed in the vmlinux binary | |
553 | Leaving it blank selects the minimal "skeleton" dtb | |
554 | ||
cfdbc2e1 VG |
555 | endmenu # "ARC Architecture Configuration" |
556 | ||
0192445c | 557 | config ARCH_FORCE_MAX_ORDER |
37eda9df | 558 | int "Maximum zone order" |
23baf831 KS |
559 | default "11" if ARC_HUGEPAGE_16M |
560 | default "10" | |
37eda9df | 561 | |
996bad6c | 562 | source "kernel/power/Kconfig" |