[linux-block.git] / arch / alpha / kernel / smp.c

// SPDX-License-Identifier: GPL-2.0
/*
 *	linux/arch/alpha/kernel/smp.c
 *
 *      2001-07-09 Phil Ezolt (Phillip.Ezolt@compaq.com)
 *            Renamed modified smp_call_function to smp_call_function_on_cpu()
 *            Created an function that conforms to the old calling convention
 *            of smp_call_function().
 *
 *            This is helpful for DCPI.
 *
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/sched/mm.h>
#include <linux/mm.h>
#include <linux/err.h>
#include <linux/threads.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <linux/cache.h>
#include <linux/profile.h>
#include <linux/bitops.h>
#include <linux/cpu.h>

#include <asm/hwrpb.h>
#include <asm/ptrace.h>
#include <linux/atomic.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>

#include "proto.h"
#include "irq_impl.h"


#define DEBUG_SMP 0
#if DEBUG_SMP
#define DBGS(args)	printk args
#else
#define DBGS(args)
#endif

/* A collection of per-processor data.  */
struct cpuinfo_alpha cpu_data[NR_CPUS];
EXPORT_SYMBOL(cpu_data);

/* A collection of single bit ipi messages.  */
static struct {
	unsigned long bits ____cacheline_aligned;
} ipi_data[NR_CPUS] __cacheline_aligned;

enum ipi_message_type {
	IPI_RESCHEDULE,
	IPI_CALL_FUNC,
	IPI_CPU_STOP,
};

/* Set to a secondary's cpuid when it comes online.  */
static int smp_secondary_alive = 0;

int smp_num_probed;		/* Internal processor count */
int smp_num_cpus = 1;		/* Number that came online.  */
EXPORT_SYMBOL(smp_num_cpus);

/*
 * Called by both boot and secondaries to move global data into
 *  per-processor storage.
 */
static inline void __init
smp_store_cpu_info(int cpuid)
{
	cpu_data[cpuid].loops_per_jiffy = loops_per_jiffy;
	cpu_data[cpuid].last_asn = ASN_FIRST_VERSION;
	cpu_data[cpuid].need_new_asn = 0;
	cpu_data[cpuid].asn_lock = 0;
}

/*
 * Ideally sets up per-cpu profiling hooks.  Doesn't do much now...
 */
static inline void __init
smp_setup_percpu_timer(int cpuid)
{
	cpu_data[cpuid].prof_counter = 1;
	cpu_data[cpuid].prof_multiplier = 1;
}

static void __init
wait_boot_cpu_to_stop(int cpuid)
{
	unsigned long stop = jiffies + 10*HZ;

	while (time_before(jiffies, stop)) {
	        if (!smp_secondary_alive)
			return;
		barrier();
	}

	printk("wait_boot_cpu_to_stop: FAILED on CPU %d, hanging now\n", cpuid);
	for (;;)
		barrier();
}

/*
 * Where secondaries begin a life of C.
 */
void __init
smp_callin(void)
{
	int cpuid = hard_smp_processor_id();

	if (cpu_online(cpuid)) {
		printk("??, cpu 0x%x already present??\n", cpuid);
		BUG();
	}
	set_cpu_online(cpuid, true);

	/* Turn on machine checks.  */
	wrmces(7);

	/* Set trap vectors.  */
	trap_init();

	/* Set interrupt vector.  */
	wrent(entInt, 0);

	/* Get our local ticker going. */
	smp_setup_percpu_timer(cpuid);
	init_clockevent();

	/* Call platform-specific callin, if specified */
	if (alpha_mv.smp_callin)
		alpha_mv.smp_callin();

	/* All kernel threads share the same mm context.  */
	mmgrab(&init_mm);
	current->active_mm = &init_mm;

	/* inform the notifiers about the new cpu */
	notify_cpu_starting(cpuid);

	/* Must have completely accurate bogos.  */
	local_irq_enable();

	/* Wait boot CPU to stop with irq enabled before running
	   calibrate_delay. */
	wait_boot_cpu_to_stop(cpuid);
	mb();
	calibrate_delay();

	smp_store_cpu_info(cpuid);
	/* Allow master to continue only after we written loops_per_jiffy.  */
	wmb();
	smp_secondary_alive = 1;

	DBGS(("smp_callin: commencing CPU %d current %p active_mm %p\n",
	      cpuid, current, current->active_mm));

	preempt_disable();
	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
}

/* Wait until hwrpb->txrdy is clear for cpu.  Return -1 on timeout.  */
static int
wait_for_txrdy (unsigned long cpumask)
{
	unsigned long timeout;

	if (!(hwrpb->txrdy & cpumask))
		return 0;

	timeout = jiffies + 10*HZ;
	while (time_before(jiffies, timeout)) {
		if (!(hwrpb->txrdy & cpumask))
			return 0;
		udelay(10);
		barrier();
	}

	return -1;
}

/*
 * Send a message to a secondary's console.  "START" is one such
 * interesting message.  ;-)
 */
static void
send_secondary_console_msg(char *str, int cpuid)
{
	struct percpu_struct *cpu;
	register char *cp1, *cp2;
	unsigned long cpumask;
	size_t len;

	cpu = (struct percpu_struct *)
		((char*)hwrpb
		 + hwrpb->processor_offset
		 + cpuid * hwrpb->processor_size);

	cpumask = (1UL << cpuid);
	if (wait_for_txrdy(cpumask))
		goto timeout;

	cp2 = str;
	len = strlen(cp2);
	*(unsigned int *)&cpu->ipc_buffer[0] = len;
	cp1 = (char *) &cpu->ipc_buffer[1];
	memcpy(cp1, cp2, len);

	/* atomic test and set */
	wmb();
	set_bit(cpuid, &hwrpb->rxrdy);

	if (wait_for_txrdy(cpumask))
		goto timeout;
	return;

 timeout:
	printk("Processor %x not ready\n", cpuid);
}

/*
 * A secondary console wants to send a message.  Receive it.
 */
static void
recv_secondary_console_msg(void)
{
	int mycpu, i, cnt;
	unsigned long txrdy = hwrpb->txrdy;
	char *cp1, *cp2, buf[80];
	struct percpu_struct *cpu;

	DBGS(("recv_secondary_console_msg: TXRDY 0x%lx.\n", txrdy));

	mycpu = hard_smp_processor_id();

	for (i = 0; i < NR_CPUS; i++) {
		if (!(txrdy & (1UL << i)))
			continue;

		DBGS(("recv_secondary_console_msg: "
		      "TXRDY contains CPU %d.\n", i));

		cpu = (struct percpu_struct *)
		  ((char*)hwrpb
		   + hwrpb->processor_offset
		   + i * hwrpb->processor_size);

 		DBGS(("recv_secondary_console_msg: on %d from %d"
		      " HALT_REASON 0x%lx FLAGS 0x%lx\n",
		      mycpu, i, cpu->halt_reason, cpu->flags));

		cnt = cpu->ipc_buffer[0] >> 32;
		if (cnt <= 0 || cnt >= 80)
			strcpy(buf, "<<< BOGUS MSG >>>");
		else {
			cp1 = (char *) &cpu->ipc_buffer[1];
			cp2 = buf;
			memcpy(cp2, cp1, cnt);
			cp2[cnt] = '\0';
			
			while ((cp2 = strchr(cp2, '\r')) != 0) {
				*cp2 = ' ';
				if (cp2[1] == '\n')
					cp2[1] = ' ';
			}
		}

		DBGS((KERN_INFO "recv_secondary_console_msg: on %d "
		      "message is '%s'\n", mycpu, buf));
	}

	hwrpb->txrdy = 0;
}

/*
 * Convince the console to have a secondary cpu begin execution.
 */
static int
secondary_cpu_start(int cpuid, struct task_struct *idle)
{
	struct percpu_struct *cpu;
	struct pcb_struct *hwpcb, *ipcb;
	unsigned long timeout;
	  
	cpu = (struct percpu_struct *)
		((char*)hwrpb
		 + hwrpb->processor_offset
		 + cpuid * hwrpb->processor_size);
	hwpcb = (struct pcb_struct *) cpu->hwpcb;
	ipcb = &task_thread_info(idle)->pcb;

	/* Initialize the CPU's HWPCB to something just good enough for
	   us to get started.  Immediately after starting, we'll swpctx
	   to the target idle task's pcb.  Reuse the stack in the mean
	   time.  Precalculate the target PCBB.  */
	hwpcb->ksp = (unsigned long)ipcb + sizeof(union thread_union) - 16;
	hwpcb->usp = 0;
	hwpcb->ptbr = ipcb->ptbr;
	hwpcb->pcc = 0;
	hwpcb->asn = 0;
	hwpcb->unique = virt_to_phys(ipcb);
	hwpcb->flags = ipcb->flags;
	hwpcb->res1 = hwpcb->res2 = 0;

#if 0
	DBGS(("KSP 0x%lx PTBR 0x%lx VPTBR 0x%lx UNIQUE 0x%lx\n",
	      hwpcb->ksp, hwpcb->ptbr, hwrpb->vptb, hwpcb->unique));
#endif
	DBGS(("Starting secondary cpu %d: state 0x%lx pal_flags 0x%lx\n",
	      cpuid, idle->state, ipcb->flags));

	/* Setup HWRPB fields that SRM uses to activate secondary CPU */
	hwrpb->CPU_restart = __smp_callin;
	hwrpb->CPU_restart_data = (unsigned long) __smp_callin;

	/* Recalculate and update the HWRPB checksum */
	hwrpb_update_checksum(hwrpb);

	/*
	 * Send a "start" command to the specified processor.
	 */

	/* SRM III 3.4.1.3 */
	cpu->flags |= 0x22;	/* turn on Context Valid and Restart Capable */
	cpu->flags &= ~1;	/* turn off Bootstrap In Progress */
	wmb();

	send_secondary_console_msg("START\r\n", cpuid);

	/* Wait 10 seconds for an ACK from the console.  */
	timeout = jiffies + 10*HZ;
	while (time_before(jiffies, timeout)) {
		if (cpu->flags & 1)
			goto started;
		udelay(10);
		barrier();
	}
	printk(KERN_ERR "SMP: Processor %d failed to start.\n", cpuid);
	return -1;

 started:
	DBGS(("secondary_cpu_start: SUCCESS for CPU %d!!!\n", cpuid));
	return 0;
}

/*
 * Bring one cpu online.
 */
static int
smp_boot_one_cpu(int cpuid, struct task_struct *idle)
{
	unsigned long timeout;

	/* Signal the secondary to wait a moment.  */
	smp_secondary_alive = -1;

	/* Whirrr, whirrr, whirrrrrrrrr... */
	if (secondary_cpu_start(cpuid, idle))
		return -1;

	/* Notify the secondary CPU it can run calibrate_delay.  */
	mb();
	smp_secondary_alive = 0;

	/* We've been acked by the console; wait one second for
	   the task to start up for real.  */
	timeout = jiffies + 1*HZ;
	while (time_before(jiffies, timeout)) {
		if (smp_secondary_alive == 1)
			goto alive;
		udelay(10);
		barrier();
	}

	/* We failed to boot the CPU.  */

	printk(KERN_ERR "SMP: Processor %d is stuck.\n", cpuid);
	return -1;

 alive:
	/* Another "Red Snapper". */
	return 0;
}

/*
 * Called from setup_arch.  Detect an SMP system and which processors
 * are present.
 */
void __init
setup_smp(void)
{
	struct percpu_struct *cpubase, *cpu;
	unsigned long i;

	if (boot_cpuid != 0) {
		printk(KERN_WARNING "SMP: Booting off cpu %d instead of 0?\n",
		       boot_cpuid);
	}

	if (hwrpb->nr_processors > 1) {
		int boot_cpu_palrev;

		DBGS(("setup_smp: nr_processors %ld\n",
		      hwrpb->nr_processors));

		cpubase = (struct percpu_struct *)
			((char*)hwrpb + hwrpb->processor_offset);
		boot_cpu_palrev = cpubase->pal_revision;

		for (i = 0; i < hwrpb->nr_processors; i++) {
			cpu = (struct percpu_struct *)
				((char *)cpubase + i*hwrpb->processor_size);
			if ((cpu->flags & 0x1cc) == 0x1cc) {
				smp_num_probed++;
				set_cpu_possible(i, true);
				set_cpu_present(i, true);
				cpu->pal_revision = boot_cpu_palrev;
			}

			DBGS(("setup_smp: CPU %d: flags 0x%lx type 0x%lx\n",
			      i, cpu->flags, cpu->type));
			DBGS(("setup_smp: CPU %d: PAL rev 0x%lx\n",
			      i, cpu->pal_revision));
		}
	} else {
		smp_num_probed = 1;
	}

	printk(KERN_INFO "SMP: %d CPUs probed -- cpu_present_mask = %lx\n",
	       smp_num_probed, cpumask_bits(cpu_present_mask)[0]);
}

/*
 * Called by smp_init prepare the secondaries
 */
void __init
smp_prepare_cpus(unsigned int max_cpus)
{
	/* Take care of some initial bookkeeping.  */
	memset(ipi_data, 0, sizeof(ipi_data));

	current_thread_info()->cpu = boot_cpuid;

	smp_store_cpu_info(boot_cpuid);
	smp_setup_percpu_timer(boot_cpuid);

	/* Nothing to do on a UP box, or when told not to.  */
	if (smp_num_probed == 1 || max_cpus == 0) {
		init_cpu_possible(cpumask_of(boot_cpuid));
		init_cpu_present(cpumask_of(boot_cpuid));
		printk(KERN_INFO "SMP mode deactivated.\n");
		return;
	}

	printk(KERN_INFO "SMP starting up secondaries.\n");

	smp_num_cpus = smp_num_probed;
}

void
smp_prepare_boot_cpu(void)
{
}

int
__cpu_up(unsigned int cpu, struct task_struct *tidle)
{
	smp_boot_one_cpu(cpu, tidle);

	return cpu_online(cpu) ? 0 : -ENOSYS;
}

void __init
smp_cpus_done(unsigned int max_cpus)
{
	int cpu;
	unsigned long bogosum = 0;

	for(cpu = 0; cpu < NR_CPUS; cpu++) 
		if (cpu_online(cpu))
			bogosum += cpu_data[cpu].loops_per_jiffy;
	
	printk(KERN_INFO "SMP: Total of %d processors activated "
	       "(%lu.%02lu BogoMIPS).\n",
	       num_online_cpus(), 
	       (bogosum + 2500) / (500000/HZ),
	       ((bogosum + 2500) / (5000/HZ)) % 100);
}

int
setup_profiling_timer(unsigned int multiplier)
{
	return -EINVAL;
}

static void
send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation)
{
	int i;

	mb();
	for_each_cpu(i, to_whom)
		set_bit(operation, &ipi_data[i].bits);

	mb();
	for_each_cpu(i, to_whom)
		wripir(i);
}

void
handle_ipi(struct pt_regs *regs)
{
	int this_cpu = smp_processor_id();
	unsigned long *pending_ipis = &ipi_data[this_cpu].bits;
	unsigned long ops;

#if 0
	DBGS(("handle_ipi: on CPU %d ops 0x%lx PC 0x%lx\n",
	      this_cpu, *pending_ipis, regs->pc));
#endif

	mb();	/* Order interrupt and bit testing. */
	while ((ops = xchg(pending_ipis, 0)) != 0) {
	  mb();	/* Order bit clearing and data access. */
	  do {
		unsigned long which;

		which = ops & -ops;
		ops &= ~which;
		which = __ffs(which);

		switch (which) {
		case IPI_RESCHEDULE:
			scheduler_ipi();
			break;

		case IPI_CALL_FUNC:
			generic_smp_call_function_interrupt();
			break;

		case IPI_CPU_STOP:
			halt();

		default:
			printk(KERN_CRIT "Unknown IPI on CPU %d: %lu\n",
			       this_cpu, which);
			break;
		}
	  } while (ops);

	  mb();	/* Order data access and bit testing. */
	}

	cpu_data[this_cpu].ipi_count++;

	if (hwrpb->txrdy)
		recv_secondary_console_msg();
}

void
smp_send_reschedule(int cpu)
{
#ifdef DEBUG_IPI_MSG
	if (cpu == hard_smp_processor_id())
		printk(KERN_WARNING
		       "smp_send_reschedule: Sending IPI to self.\n");
#endif
	send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
}

void
smp_send_stop(void)
{
	cpumask_t to_whom;
	cpumask_copy(&to_whom, cpu_possible_mask);
	cpumask_clear_cpu(smp_processor_id(), &to_whom);
#ifdef DEBUG_IPI_MSG
	if (hard_smp_processor_id() != boot_cpu_id)
		printk(KERN_WARNING "smp_send_stop: Not on boot cpu.\n");
#endif
	send_ipi_message(&to_whom, IPI_CPU_STOP);
}

void arch_send_call_function_ipi_mask(const struct cpumask *mask)
{
	send_ipi_message(mask, IPI_CALL_FUNC);
}

void arch_send_call_function_single_ipi(int cpu)
{
	send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
}

static void
ipi_imb(void *ignored)
{
	imb();
}

void
smp_imb(void)
{
	/* Must wait other processors to flush their icache before continue. */
	if (on_each_cpu(ipi_imb, NULL, 1))
		printk(KERN_CRIT "smp_imb: timed out\n");
}
EXPORT_SYMBOL(smp_imb);

static void
ipi_flush_tlb_all(void *ignored)
{
	tbia();
}

void
flush_tlb_all(void)
{
	/* Although we don't have any data to pass, we do want to
	   synchronize with the other processors.  */
	if (on_each_cpu(ipi_flush_tlb_all, NULL, 1)) {
		printk(KERN_CRIT "flush_tlb_all: timed out\n");
	}
}

#define asn_locked() (cpu_data[smp_processor_id()].asn_lock)

static void
ipi_flush_tlb_mm(void *x)
{
	struct mm_struct *mm = (struct mm_struct *) x;
	if (mm == current->active_mm && !asn_locked())
		flush_tlb_current(mm);
	else
		flush_tlb_other(mm);
}

void
flush_tlb_mm(struct mm_struct *mm)
{
	preempt_disable();

	if (mm == current->active_mm) {
		flush_tlb_current(mm);
		if (atomic_read(&mm->mm_users) <= 1) {
			int cpu, this_cpu = smp_processor_id();
			for (cpu = 0; cpu < NR_CPUS; cpu++) {
				if (!cpu_online(cpu) || cpu == this_cpu)
					continue;
				if (mm->context[cpu])
					mm->context[cpu] = 0;
			}
			preempt_enable();
			return;
		}
	}

	if (smp_call_function(ipi_flush_tlb_mm, mm, 1)) {
		printk(KERN_CRIT "flush_tlb_mm: timed out\n");
	}

	preempt_enable();
}
EXPORT_SYMBOL(flush_tlb_mm);

struct flush_tlb_page_struct {
	struct vm_area_struct *vma;
	struct mm_struct *mm;
	unsigned long addr;
};

static void
ipi_flush_tlb_page(void *x)
{
	struct flush_tlb_page_struct *data = (struct flush_tlb_page_struct *)x;
	struct mm_struct * mm = data->mm;

	if (mm == current->active_mm && !asn_locked())
		flush_tlb_current_page(mm, data->vma, data->addr);
	else
		flush_tlb_other(mm);
}

void
flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
{
	struct flush_tlb_page_struct data;
	struct mm_struct *mm = vma->vm_mm;

	preempt_disable();

	if (mm == current->active_mm) {
		flush_tlb_current_page(mm, vma, addr);
		if (atomic_read(&mm->mm_users) <= 1) {
			int cpu, this_cpu = smp_processor_id();
			for (cpu = 0; cpu < NR_CPUS; cpu++) {
				if (!cpu_online(cpu) || cpu == this_cpu)
					continue;
				if (mm->context[cpu])
					mm->context[cpu] = 0;
			}
			preempt_enable();
			return;
		}
	}

	data.vma = vma;
	data.mm = mm;
	data.addr = addr;

	if (smp_call_function(ipi_flush_tlb_page, &data, 1)) {
		printk(KERN_CRIT "flush_tlb_page: timed out\n");
	}

	preempt_enable();
}
EXPORT_SYMBOL(flush_tlb_page);

void
flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
{
	/* On the Alpha we always flush the whole user tlb.  */
	flush_tlb_mm(vma->vm_mm);
}
EXPORT_SYMBOL(flush_tlb_range);

static void
ipi_flush_icache_page(void *x)
{
	struct mm_struct *mm = (struct mm_struct *) x;
	if (mm == current->active_mm && !asn_locked())
		__load_new_mm_context(mm);
	else
		flush_tlb_other(mm);
}

void
flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
			unsigned long addr, int len)
{
	struct mm_struct *mm = vma->vm_mm;

	if ((vma->vm_flags & VM_EXEC) == 0)
		return;

	preempt_disable();

	if (mm == current->active_mm) {
		__load_new_mm_context(mm);
		if (atomic_read(&mm->mm_users) <= 1) {
			int cpu, this_cpu = smp_processor_id();
			for (cpu = 0; cpu < NR_CPUS; cpu++) {
				if (!cpu_online(cpu) || cpu == this_cpu)
					continue;
				if (mm->context[cpu])
					mm->context[cpu] = 0;
			}
			preempt_enable();
			return;
		}
	}

	if (smp_call_function(ipi_flush_icache_page, mm, 1)) {
		printk(KERN_CRIT "flush_icache_page: timed out\n");
	}

	preempt_enable();
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* linux/arch/alpha/kernel/smp.c
	4	*
	5	* 2001-07-09 Phil Ezolt (Phillip.Ezolt@compaq.com)
	6	* Renamed modified smp_call_function to smp_call_function_on_cpu()
	7	* Created an function that conforms to the old calling convention
	8	* of smp_call_function().
	9	*
	10	* This is helpful for DCPI.
	11	*
	12	*/
	13
	14	#include <linux/errno.h>
	15	#include <linux/kernel.h>
	16	#include <linux/kernel_stat.h>
	17	#include <linux/module.h>
68e21be2	18	#include <linux/sched/mm.h>
1da177e4	19	#include <linux/mm.h>
4e950f6f	20	#include <linux/err.h>
1da177e4 LT	21	#include <linux/threads.h>
1da177e4 LT	22	#include <linux/smp.h>
1da177e4 LT	23	#include <linux/interrupt.h>
	24	#include <linux/init.h>
	25	#include <linux/delay.h>
	26	#include <linux/spinlock.h>
	27	#include <linux/irq.h>
	28	#include <linux/cache.h>
	29	#include <linux/profile.h>
	30	#include <linux/bitops.h>
574f34ce	31	#include <linux/cpu.h>
1da177e4 LT	32
	33	#include <asm/hwrpb.h>
	34	#include <asm/ptrace.h>
60063497	35	#include <linux/atomic.h>
1da177e4 LT	36
	37	#include <asm/io.h>
	38	#include <asm/irq.h>
	39	#include <asm/pgtable.h>
	40	#include <asm/pgalloc.h>
	41	#include <asm/mmu_context.h>
	42	#include <asm/tlbflush.h>
	43
	44	#include "proto.h"
	45	#include "irq_impl.h"
	46
	47
	48	#define DEBUG_SMP 0
	49	#if DEBUG_SMP
	50	#define DBGS(args) printk args
	51	#else
	52	#define DBGS(args)
	53	#endif
	54
	55	/* A collection of per-processor data. */
	56	struct cpuinfo_alpha cpu_data[NR_CPUS];
cff52daf	57	EXPORT_SYMBOL(cpu_data);
1da177e4 LT	58
	59	/* A collection of single bit ipi messages. */
	60	static struct {
	61	unsigned long bits ____cacheline_aligned;
	62	} ipi_data[NR_CPUS] __cacheline_aligned;
	63
	64	enum ipi_message_type {
	65	IPI_RESCHEDULE,
	66	IPI_CALL_FUNC,
	67	IPI_CPU_STOP,
	68	};
	69
	70	/* Set to a secondary's cpuid when it comes online. */
f8d6c8d9	71	static int smp_secondary_alive = 0;
1da177e4	72
1da177e4 LT	73	int smp_num_probed; /* Internal processor count */
1da177e4 LT	74	int smp_num_cpus = 1; /* Number that came online. */
cff52daf	75	EXPORT_SYMBOL(smp_num_cpus);
1da177e4	76
1da177e4 LT	77	/*
	78	* Called by both boot and secondaries to move global data into
	79	* per-processor storage.
	80	*/
	81	static inline void __init
	82	smp_store_cpu_info(int cpuid)
	83	{
	84	cpu_data[cpuid].loops_per_jiffy = loops_per_jiffy;
	85	cpu_data[cpuid].last_asn = ASN_FIRST_VERSION;
	86	cpu_data[cpuid].need_new_asn = 0;
	87	cpu_data[cpuid].asn_lock = 0;
	88	}
	89
	90	/*
	91	* Ideally sets up per-cpu profiling hooks. Doesn't do much now...
	92	*/
	93	static inline void __init
	94	smp_setup_percpu_timer(int cpuid)
	95	{
	96	cpu_data[cpuid].prof_counter = 1;
	97	cpu_data[cpuid].prof_multiplier = 1;
	98	}
	99
	100	static void __init
	101	wait_boot_cpu_to_stop(int cpuid)
	102	{
	103	unsigned long stop = jiffies + 10*HZ;
	104
	105	while (time_before(jiffies, stop)) {
	106	if (!smp_secondary_alive)
	107	return;
	108	barrier();
	109	}
	110
	111	printk("wait_boot_cpu_to_stop: FAILED on CPU %d, hanging now\n", cpuid);
	112	for (;;)
	113	barrier();
	114	}
	115
	116	/*
	117	* Where secondaries begin a life of C.
	118	*/
69f06782	119	void __init
1da177e4 LT	120	smp_callin(void)
	121	{
	122	int cpuid = hard_smp_processor_id();
	123
1371be0f	124	if (cpu_online(cpuid)) {
1da177e4 LT	125	printk("??, cpu 0x%x already present??\n", cpuid);
	126	BUG();
	127	}
1371be0f	128	set_cpu_online(cpuid, true);
1da177e4 LT	129
	130	/* Turn on machine checks. */
	131	wrmces(7);
	132
	133	/* Set trap vectors. */
	134	trap_init();
	135
	136	/* Set interrupt vector. */
	137	wrent(entInt, 0);
	138
	139	/* Get our local ticker going. */
	140	smp_setup_percpu_timer(cpuid);
a1659d6d	141	init_clockevent();
1da177e4 LT	142
1da177e4 LT	143	/* Call platform-specific callin, if specified */
a1659d6d RH	144	if (alpha_mv.smp_callin)
a1659d6d RH	145	alpha_mv.smp_callin();
1da177e4 LT	146
1da177e4 LT	147	/* All kernel threads share the same mm context. */
f1f10076	148	mmgrab(&init_mm);
1da177e4 LT	149	current->active_mm = &init_mm;
1da177e4 LT	150
e545a614 MS	151	/* inform the notifiers about the new cpu */
	152	notify_cpu_starting(cpuid);
	153
1da177e4 LT	154	/* Must have completely accurate bogos. */
	155	local_irq_enable();
	156
	157	/* Wait boot CPU to stop with irq enabled before running
	158	calibrate_delay. */
	159	wait_boot_cpu_to_stop(cpuid);
	160	mb();
	161	calibrate_delay();
	162
	163	smp_store_cpu_info(cpuid);
	164	/* Allow master to continue only after we written loops_per_jiffy. */
	165	wmb();
	166	smp_secondary_alive = 1;
	167
	168	DBGS(("smp_callin: commencing CPU %d current %p active_mm %p\n",
	169	cpuid, current, current->active_mm));
	170
6a6c0272	171	preempt_disable();
fc6d73d6	172	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1da177e4 LT	173	}
	174
	175	/* Wait until hwrpb->txrdy is clear for cpu. Return -1 on timeout. */
f8d6c8d9	176	static int
1da177e4 LT	177	wait_for_txrdy (unsigned long cpumask)
	178	{
	179	unsigned long timeout;
	180
	181	if (!(hwrpb->txrdy & cpumask))
	182	return 0;
	183
	184	timeout = jiffies + 10*HZ;
	185	while (time_before(jiffies, timeout)) {
	186	if (!(hwrpb->txrdy & cpumask))
	187	return 0;
	188	udelay(10);
	189	barrier();
	190	}
	191
	192	return -1;
	193	}
	194
	195	/*
	196	* Send a message to a secondary's console. "START" is one such
	197	* interesting message. ;-)
	198	*/
ab39c77c	199	static void
1da177e4 LT	200	send_secondary_console_msg(char *str, int cpuid)
	201	{
	202	struct percpu_struct *cpu;
	203	register char cp1, cp2;
	204	unsigned long cpumask;
	205	size_t len;
	206
	207	cpu = (struct percpu_struct *)
	208	((char*)hwrpb
	209	+ hwrpb->processor_offset
	210	+ cpuid * hwrpb->processor_size);
	211
	212	cpumask = (1UL << cpuid);
	213	if (wait_for_txrdy(cpumask))
	214	goto timeout;
	215
	216	cp2 = str;
	217	len = strlen(cp2);
	218	(unsigned int )&cpu->ipc_buffer[0] = len;
	219	cp1 = (char *) &cpu->ipc_buffer[1];
	220	memcpy(cp1, cp2, len);
	221
	222	/* atomic test and set */
	223	wmb();
	224	set_bit(cpuid, &hwrpb->rxrdy);
	225
	226	if (wait_for_txrdy(cpumask))
	227	goto timeout;
	228	return;
	229
	230	timeout:
	231	printk("Processor %x not ready\n", cpuid);
	232	}
	233
	234	/*
	235	* A secondary console wants to send a message. Receive it.
	236	*/
	237	static void
	238	recv_secondary_console_msg(void)
	239	{
	240	int mycpu, i, cnt;
	241	unsigned long txrdy = hwrpb->txrdy;
	242	char cp1, cp2, buf[80];
	243	struct percpu_struct *cpu;
	244
	245	DBGS(("recv_secondary_console_msg: TXRDY 0x%lx.\n", txrdy));
	246
	247	mycpu = hard_smp_processor_id();
	248
	249	for (i = 0; i < NR_CPUS; i++) {
	250	if (!(txrdy & (1UL << i)))
	251	continue;
	252
	253	DBGS(("recv_secondary_console_msg: "
	254	"TXRDY contains CPU %d.\n", i));
	255
	256	cpu = (struct percpu_struct *)
	257	((char*)hwrpb
	258	+ hwrpb->processor_offset
	259	+ i * hwrpb->processor_size);
	260
	261	DBGS(("recv_secondary_console_msg: on %d from %d"
	262	" HALT_REASON 0x%lx FLAGS 0x%lx\n",
	263	mycpu, i, cpu->halt_reason, cpu->flags));
264
265	cnt = cpu->ipc_buffer[0] >> 32;
266	if (cnt <= 0 \|\| cnt >= 80)
267	strcpy(buf, "<<< BOGUS MSG >>>");
268	else {
91b678c8	269	cp1 = (char *) &cpu->ipc_buffer[1];
1da177e4	270	cp2 = buf;
00ee0309 CG	271	memcpy(cp2, cp1, cnt);
00ee0309 CG	272	cp2[cnt] = '\0';
1da177e4 LT	273
	274	while ((cp2 = strchr(cp2, '\r')) != 0) {
	275	*cp2 = ' ';
	276	if (cp2[1] == '\n')
	277	cp2[1] = ' ';
	278	}
	279	}
	280
	281	DBGS((KERN_INFO "recv_secondary_console_msg: on %d "
	282	"message is '%s'\n", mycpu, buf));
	283	}
	284
	285	hwrpb->txrdy = 0;
	286	}
	287
	288	/*
	289	* Convince the console to have a secondary cpu begin execution.
	290	*/
ab39c77c	291	static int
1da177e4 LT	292	secondary_cpu_start(int cpuid, struct task_struct *idle)
	293	{
	294	struct percpu_struct *cpu;
	295	struct pcb_struct hwpcb, ipcb;
	296	unsigned long timeout;
	297
	298	cpu = (struct percpu_struct *)
	299	((char*)hwrpb
	300	+ hwrpb->processor_offset
	301	+ cpuid * hwrpb->processor_size);
	302	hwpcb = (struct pcb_struct *) cpu->hwpcb;
37bfbaf9	303	ipcb = &task_thread_info(idle)->pcb;
1da177e4 LT	304
	305	/* Initialize the CPU's HWPCB to something just good enough for
	306	us to get started. Immediately after starting, we'll swpctx
	307	to the target idle task's pcb. Reuse the stack in the mean
	308	time. Precalculate the target PCBB. */
	309	hwpcb->ksp = (unsigned long)ipcb + sizeof(union thread_union) - 16;
	310	hwpcb->usp = 0;
	311	hwpcb->ptbr = ipcb->ptbr;
	312	hwpcb->pcc = 0;
	313	hwpcb->asn = 0;
	314	hwpcb->unique = virt_to_phys(ipcb);
	315	hwpcb->flags = ipcb->flags;
	316	hwpcb->res1 = hwpcb->res2 = 0;
	317
	318	#if 0
	319	DBGS(("KSP 0x%lx PTBR 0x%lx VPTBR 0x%lx UNIQUE 0x%lx\n",
	320	hwpcb->ksp, hwpcb->ptbr, hwrpb->vptb, hwpcb->unique));
	321	#endif
	322	DBGS(("Starting secondary cpu %d: state 0x%lx pal_flags 0x%lx\n",
	323	cpuid, idle->state, ipcb->flags));
	324
	325	/* Setup HWRPB fields that SRM uses to activate secondary CPU */
	326	hwrpb->CPU_restart = __smp_callin;
	327	hwrpb->CPU_restart_data = (unsigned long) __smp_callin;
	328
	329	/* Recalculate and update the HWRPB checksum */
	330	hwrpb_update_checksum(hwrpb);
	331
	332	/*
	333	* Send a "start" command to the specified processor.
	334	*/
	335
	336	/* SRM III 3.4.1.3 */
	337	cpu->flags \|= 0x22; /* turn on Context Valid and Restart Capable */
	338	cpu->flags &= ~1; /* turn off Bootstrap In Progress */
	339	wmb();
	340
	341	send_secondary_console_msg("START\r\n", cpuid);
	342
	343	/* Wait 10 seconds for an ACK from the console. */
	344	timeout = jiffies + 10*HZ;
	345	while (time_before(jiffies, timeout)) {
	346	if (cpu->flags & 1)
	347	goto started;
	348	udelay(10);
	349	barrier();
	350	}
	351	printk(KERN_ERR "SMP: Processor %d failed to start.\n", cpuid);
	352	return -1;
	353
	354	started:
	355	DBGS(("secondary_cpu_start: SUCCESS for CPU %d!!!\n", cpuid));
	356	return 0;
	357	}
	358
	359	/*
	360	* Bring one cpu online.
	361	*/
ab39c77c	362	static int
2ec9415c	363	smp_boot_one_cpu(int cpuid, struct task_struct *idle)
1da177e4	364	{
1da177e4 LT	365	unsigned long timeout;
1da177e4 LT	366
1da177e4 LT	367	/* Signal the secondary to wait a moment. */
	368	smp_secondary_alive = -1;
	369
	370	/* Whirrr, whirrr, whirrrrrrrrr... */
	371	if (secondary_cpu_start(cpuid, idle))
	372	return -1;
	373
	374	/* Notify the secondary CPU it can run calibrate_delay. */
	375	mb();
	376	smp_secondary_alive = 0;
	377
	378	/* We've been acked by the console; wait one second for
	379	the task to start up for real. */
	380	timeout = jiffies + 1*HZ;
	381	while (time_before(jiffies, timeout)) {
	382	if (smp_secondary_alive == 1)
	383	goto alive;
	384	udelay(10);
	385	barrier();
	386	}
	387
	388	/* We failed to boot the CPU. */
	389
	390	printk(KERN_ERR "SMP: Processor %d is stuck.\n", cpuid);
	391	return -1;
	392
	393	alive:
	394	/* Another "Red Snapper". */
	395	return 0;
	396	}
	397
	398	/*
	399	* Called from setup_arch. Detect an SMP system and which processors
	400	* are present.
	401	*/
	402	void __init
	403	setup_smp(void)
	404	{
	405	struct percpu_struct cpubase, cpu;
	406	unsigned long i;
	407
	408	if (boot_cpuid != 0) {
	409	printk(KERN_WARNING "SMP: Booting off cpu %d instead of 0?\n",
	410	boot_cpuid);
	411	}
	412
	413	if (hwrpb->nr_processors > 1) {
	414	int boot_cpu_palrev;
	415
	416	DBGS(("setup_smp: nr_processors %ld\n",
	417	hwrpb->nr_processors));
	418
	419	cpubase = (struct percpu_struct *)
	420	((char*)hwrpb + hwrpb->processor_offset);
	421	boot_cpu_palrev = cpubase->pal_revision;
	422
	423	for (i = 0; i < hwrpb->nr_processors; i++) {
	424	cpu = (struct percpu_struct *)
	425	((char )cpubase + ihwrpb->processor_size);
	426	if ((cpu->flags & 0x1cc) == 0x1cc) {
	427	smp_num_probed++;
1371be0f RR	428	set_cpu_possible(i, true);
1371be0f RR	429	set_cpu_present(i, true);
1da177e4 LT	430	cpu->pal_revision = boot_cpu_palrev;
	431	}
	432
	433	DBGS(("setup_smp: CPU %d: flags 0x%lx type 0x%lx\n",
	434	i, cpu->flags, cpu->type));
	435	DBGS(("setup_smp: CPU %d: PAL rev 0x%lx\n",
	436	i, cpu->pal_revision));
	437	}
	438	} else {
	439	smp_num_probed = 1;
1da177e4	440	}
1da177e4	441
5f054e31	442	printk(KERN_INFO "SMP: %d CPUs probed -- cpu_present_mask = %lx\n",
81740fc6	443	smp_num_probed, cpumask_bits(cpu_present_mask)[0]);
1da177e4 LT	444	}
	445
	446	/*
	447	* Called by smp_init prepare the secondaries
	448	*/
	449	void __init
	450	smp_prepare_cpus(unsigned int max_cpus)
	451	{
1da177e4 LT	452	/* Take care of some initial bookkeeping. */
	453	memset(ipi_data, 0, sizeof(ipi_data));
	454
	455	current_thread_info()->cpu = boot_cpuid;
	456
	457	smp_store_cpu_info(boot_cpuid);
	458	smp_setup_percpu_timer(boot_cpuid);
	459
	460	/* Nothing to do on a UP box, or when told not to. */
	461	if (smp_num_probed == 1 \|\| max_cpus == 0) {
1371be0f RR	462	init_cpu_possible(cpumask_of(boot_cpuid));
1371be0f RR	463	init_cpu_present(cpumask_of(boot_cpuid));
1da177e4 LT	464	printk(KERN_INFO "SMP mode deactivated.\n");
	465	return;
	466	}
	467
	468	printk(KERN_INFO "SMP starting up secondaries.\n");
	469
328c2a8a	470	smp_num_cpus = smp_num_probed;
1da177e4 LT	471	}
1da177e4 LT	472
f8d6c8d9	473	void
1da177e4 LT	474	smp_prepare_boot_cpu(void)
1da177e4 LT	475	{
1da177e4 LT	476	}
1da177e4 LT	477
ab39c77c	478	int
8239c25f	479	__cpu_up(unsigned int cpu, struct task_struct *tidle)
1da177e4	480	{
2ec9415c	481	smp_boot_one_cpu(cpu, tidle);
1da177e4 LT	482
	483	return cpu_online(cpu) ? 0 : -ENOSYS;
	484	}
	485
	486	void __init
	487	smp_cpus_done(unsigned int max_cpus)
	488	{
	489	int cpu;
	490	unsigned long bogosum = 0;
	491
	492	for(cpu = 0; cpu < NR_CPUS; cpu++)
	493	if (cpu_online(cpu))
	494	bogosum += cpu_data[cpu].loops_per_jiffy;
	495
	496	printk(KERN_INFO "SMP: Total of %d processors activated "
	497	"(%lu.%02lu BogoMIPS).\n",
	498	num_online_cpus(),
	499	(bogosum + 2500) / (500000/HZ),
	500	((bogosum + 2500) / (5000/HZ)) % 100);
	501	}
	502
ed5f6561	503	int
1da177e4 LT	504	setup_profiling_timer(unsigned int multiplier)
	505	{
	506	return -EINVAL;
	507	}
	508
1da177e4	509	static void
81065e4f	510	send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation)
1da177e4 LT	511	{
	512	int i;
	513
	514	mb();
81065e4f	515	for_each_cpu(i, to_whom)
1da177e4 LT	516	set_bit(operation, &ipi_data[i].bits);
	517
	518	mb();
81065e4f	519	for_each_cpu(i, to_whom)
1da177e4 LT	520	wripir(i);
	521	}
	522
1da177e4 LT	523	void
	524	handle_ipi(struct pt_regs *regs)
	525	{
	526	int this_cpu = smp_processor_id();
	527	unsigned long *pending_ipis = &ipi_data[this_cpu].bits;
	528	unsigned long ops;
	529
	530	#if 0
	531	DBGS(("handle_ipi: on CPU %d ops 0x%lx PC 0x%lx\n",
	532	this_cpu, *pending_ipis, regs->pc));
	533	#endif
	534
	535	mb(); /* Order interrupt and bit testing. */
	536	while ((ops = xchg(pending_ipis, 0)) != 0) {
	537	mb(); /* Order bit clearing and data access. */
	538	do {
	539	unsigned long which;
	540
	541	which = ops & -ops;
	542	ops &= ~which;
	543	which = __ffs(which);
	544
	545	switch (which) {
	546	case IPI_RESCHEDULE:
184748cc	547	scheduler_ipi();
1da177e4 LT	548	break;
	549
	550	case IPI_CALL_FUNC:
c524a1d8 JA	551	generic_smp_call_function_interrupt();
	552	break;
	553
1da177e4 LT	554	case IPI_CPU_STOP:
	555	halt();
	556
	557	default:
	558	printk(KERN_CRIT "Unknown IPI on CPU %d: %lu\n",
	559	this_cpu, which);
	560	break;
	561	}
	562	} while (ops);
	563
	564	mb(); /* Order data access and bit testing. */
	565	}
	566
	567	cpu_data[this_cpu].ipi_count++;
	568
	569	if (hwrpb->txrdy)
	570	recv_secondary_console_msg();
	571	}
	572
	573	void
	574	smp_send_reschedule(int cpu)
	575	{
	576	#ifdef DEBUG_IPI_MSG
	577	if (cpu == hard_smp_processor_id())
	578	printk(KERN_WARNING
	579	"smp_send_reschedule: Sending IPI to self.\n");
	580	#endif
81065e4f	581	send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
1da177e4 LT	582	}
	583
	584	void
	585	smp_send_stop(void)
	586	{
81740fc6 KM	587	cpumask_t to_whom;
	588	cpumask_copy(&to_whom, cpu_possible_mask);
	589	cpumask_clear_cpu(smp_processor_id(), &to_whom);
1da177e4 LT	590	#ifdef DEBUG_IPI_MSG
	591	if (hard_smp_processor_id() != boot_cpu_id)
	592	printk(KERN_WARNING "smp_send_stop: Not on boot cpu.\n");
	593	#endif
81065e4f	594	send_ipi_message(&to_whom, IPI_CPU_STOP);
1da177e4 LT	595	}
1da177e4 LT	596
81065e4f	597	void arch_send_call_function_ipi_mask(const struct cpumask *mask)
1da177e4	598	{
c524a1d8	599	send_ipi_message(mask, IPI_CALL_FUNC);
1da177e4 LT	600	}
1da177e4 LT	601
c524a1d8	602	void arch_send_call_function_single_ipi(int cpu)
1da177e4	603	{
614aab52	604	send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
1da177e4 LT	605	}
	606
	607	static void
	608	ipi_imb(void *ignored)
	609	{
	610	imb();
	611	}
	612
	613	void
	614	smp_imb(void)
	615	{
	616	/* Must wait other processors to flush their icache before continue. */
15c8b6c1	617	if (on_each_cpu(ipi_imb, NULL, 1))
1da177e4 LT	618	printk(KERN_CRIT "smp_imb: timed out\n");
1da177e4 LT	619	}
cff52daf	620	EXPORT_SYMBOL(smp_imb);
1da177e4 LT	621
	622	static void
	623	ipi_flush_tlb_all(void *ignored)
	624	{
	625	tbia();
	626	}
	627
	628	void
	629	flush_tlb_all(void)
	630	{
	631	/* Although we don't have any data to pass, we do want to
	632	synchronize with the other processors. */
15c8b6c1	633	if (on_each_cpu(ipi_flush_tlb_all, NULL, 1)) {
1da177e4 LT	634	printk(KERN_CRIT "flush_tlb_all: timed out\n");
	635	}
	636	}
	637
	638	#define asn_locked() (cpu_data[smp_processor_id()].asn_lock)
	639
	640	static void
	641	ipi_flush_tlb_mm(void *x)
	642	{
	643	struct mm_struct mm = (struct mm_struct ) x;
	644	if (mm == current->active_mm && !asn_locked())
	645	flush_tlb_current(mm);
	646	else
	647	flush_tlb_other(mm);
	648	}
	649
	650	void
	651	flush_tlb_mm(struct mm_struct *mm)
	652	{
	653	preempt_disable();
	654
	655	if (mm == current->active_mm) {
	656	flush_tlb_current(mm);
	657	if (atomic_read(&mm->mm_users) <= 1) {
	658	int cpu, this_cpu = smp_processor_id();
	659	for (cpu = 0; cpu < NR_CPUS; cpu++) {
	660	if (!cpu_online(cpu) \|\| cpu == this_cpu)
	661	continue;
	662	if (mm->context[cpu])
	663	mm->context[cpu] = 0;
	664	}
	665	preempt_enable();
	666	return;
	667	}
	668	}
	669
8691e5a8	670	if (smp_call_function(ipi_flush_tlb_mm, mm, 1)) {
1da177e4 LT	671	printk(KERN_CRIT "flush_tlb_mm: timed out\n");
	672	}
	673
	674	preempt_enable();
	675	}
cff52daf	676	EXPORT_SYMBOL(flush_tlb_mm);
1da177e4 LT	677
	678	struct flush_tlb_page_struct {
	679	struct vm_area_struct *vma;
	680	struct mm_struct *mm;
	681	unsigned long addr;
	682	};
	683
	684	static void
	685	ipi_flush_tlb_page(void *x)
	686	{
	687	struct flush_tlb_page_struct data = (struct flush_tlb_page_struct )x;
	688	struct mm_struct * mm = data->mm;
	689
	690	if (mm == current->active_mm && !asn_locked())
	691	flush_tlb_current_page(mm, data->vma, data->addr);
	692	else
	693	flush_tlb_other(mm);
	694	}
	695
	696	void
	697	flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
	698	{
	699	struct flush_tlb_page_struct data;
	700	struct mm_struct *mm = vma->vm_mm;
	701
	702	preempt_disable();
	703
	704	if (mm == current->active_mm) {
	705	flush_tlb_current_page(mm, vma, addr);
	706	if (atomic_read(&mm->mm_users) <= 1) {
	707	int cpu, this_cpu = smp_processor_id();
	708	for (cpu = 0; cpu < NR_CPUS; cpu++) {
	709	if (!cpu_online(cpu) \|\| cpu == this_cpu)
	710	continue;
	711	if (mm->context[cpu])
	712	mm->context[cpu] = 0;
	713	}
	714	preempt_enable();
	715	return;
	716	}
	717	}
	718
	719	data.vma = vma;
	720	data.mm = mm;
	721	data.addr = addr;
	722
8691e5a8	723	if (smp_call_function(ipi_flush_tlb_page, &data, 1)) {
1da177e4 LT	724	printk(KERN_CRIT "flush_tlb_page: timed out\n");
	725	}
	726
	727	preempt_enable();
	728	}
cff52daf	729	EXPORT_SYMBOL(flush_tlb_page);
1da177e4 LT	730
	731	void
	732	flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
	733	{
	734	/* On the Alpha we always flush the whole user tlb. */
	735	flush_tlb_mm(vma->vm_mm);
	736	}
cff52daf	737	EXPORT_SYMBOL(flush_tlb_range);
1da177e4 LT	738
	739	static void
	740	ipi_flush_icache_page(void *x)
	741	{
	742	struct mm_struct mm = (struct mm_struct ) x;
	743	if (mm == current->active_mm && !asn_locked())
	744	__load_new_mm_context(mm);
	745	else
	746	flush_tlb_other(mm);
	747	}
	748
	749	void
	750	flush_icache_user_range(struct vm_area_struct vma, struct page page,
	751	unsigned long addr, int len)
	752	{
	753	struct mm_struct *mm = vma->vm_mm;
	754
	755	if ((vma->vm_flags & VM_EXEC) == 0)
	756	return;
	757
	758	preempt_disable();
	759
	760	if (mm == current->active_mm) {
	761	__load_new_mm_context(mm);
	762	if (atomic_read(&mm->mm_users) <= 1) {
	763	int cpu, this_cpu = smp_processor_id();
	764	for (cpu = 0; cpu < NR_CPUS; cpu++) {
	765	if (!cpu_online(cpu) \|\| cpu == this_cpu)
	766	continue;
	767	if (mm->context[cpu])
	768	mm->context[cpu] = 0;
	769	}
	770	preempt_enable();
	771	return;
	772	}
	773	}
	774
8691e5a8	775	if (smp_call_function(ipi_flush_icache_page, mm, 1)) {
1da177e4 LT	776	printk(KERN_CRIT "flush_icache_page: timed out\n");
	777	}
	778
	779	preempt_enable();
	780	}