[linux-block.git] / arch / alpha / kernel / pci.c

// SPDX-License-Identifier: GPL-2.0
/*
 *	linux/arch/alpha/kernel/pci.c
 *
 * Extruded from code written by
 *	Dave Rusling (david.rusling@reo.mts.dec.com)
 *	David Mosberger (davidm@cs.arizona.edu)
 */

/* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     PCI-PCI bridges cleanup
 */
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include <asm/machvec.h>

#include "proto.h"
#include "pci_impl.h"


/*
 * Some string constants used by the various core logics. 
 */

const char *const pci_io_names[] = {
  "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
  "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
};

const char *const pci_mem_names[] = {
  "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
  "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
};

const char pci_hae0_name[] = "HAE0";

/*
 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
 * assignments.
 */

/*
 * The PCI controller list.
 */

struct pci_controller *hose_head, **hose_tail = &hose_head;
struct pci_controller *pci_isa_hose;

/*
 * Quirks.
 */

static void quirk_isa_bridge(struct pci_dev *dev)
{
	dev->class = PCI_CLASS_BRIDGE_ISA << 8;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);

static void quirk_cypress(struct pci_dev *dev)
{
	/* The Notorious Cy82C693 chip.  */

	/* The generic legacy mode IDE fixup in drivers/pci/probe.c
	   doesn't work correctly with the Cypress IDE controller as
	   it has non-standard register layout.  Fix that.  */
	if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
		dev->resource[2].start = dev->resource[3].start = 0;
		dev->resource[2].end = dev->resource[3].end = 0;
		dev->resource[2].flags = dev->resource[3].flags = 0;
		if (PCI_FUNC(dev->devfn) == 2) {
			dev->resource[0].start = 0x170;
			dev->resource[0].end = 0x177;
			dev->resource[1].start = 0x376;
			dev->resource[1].end = 0x376;
		}
	}

	/* The Cypress bridge responds on the PCI bus in the address range
	   0xffff0000-0xffffffff (conventional x86 BIOS ROM).  There is no
	   way to turn this off.  The bridge also supports several extended
	   BIOS ranges (disabled after power-up), and some consoles do turn
	   them on.  So if we use a large direct-map window, or a large SG
	   window, we must avoid the entire 0xfff00000-0xffffffff region.  */
	if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
		if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
			__direct_map_size = 0xfff00000UL - __direct_map_base;
		else {
			struct pci_controller *hose = dev->sysdata;
			struct pci_iommu_arena *pci = hose->sg_pci;
			if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
				pci->size = 0xfff00000UL - pci->dma_base;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);

/* Called for each device after PCI setup is done. */
static void pcibios_fixup_final(struct pci_dev *dev)
{
	unsigned int class = dev->class >> 8;

	if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
		dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
		isa_bridge = dev;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);

/* Just declaring that the power-of-ten prefixes are actually the
   power-of-two ones doesn't make it true :) */
#define KB			1024
#define MB			(1024*KB)
#define GB			(1024*MB)

resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
		       resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_controller *hose = dev->sysdata;
	unsigned long alignto;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		/* Make sure we start at our min on all hoses */
		if (start - hose->io_space->start < PCIBIOS_MIN_IO)
			start = PCIBIOS_MIN_IO + hose->io_space->start;

		/*
		 * Put everything into 0x00-0xff region modulo 0x400
		 */
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	}
	else if	(res->flags & IORESOURCE_MEM) {
		/* Make sure we start at our min on all hoses */
		if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
			start = PCIBIOS_MIN_MEM + hose->mem_space->start;

		/*
		 * The following holds at least for the Low Cost
		 * Alpha implementation of the PCI interface:
		 *
		 * In sparse memory address space, the first
		 * octant (16MB) of every 128MB segment is
		 * aliased to the very first 16 MB of the
		 * address space (i.e., it aliases the ISA
		 * memory address space).  Thus, we try to
		 * avoid allocating PCI devices in that range.
		 * Can be allocated in 2nd-7th octant only.
		 * Devices that need more than 112MB of
		 * address space must be accessed through
		 * dense memory space only!
		 */

		/* Align to multiple of size of minimum base.  */
		alignto = max_t(resource_size_t, 0x1000, align);
		start = ALIGN(start, alignto);
		if (hose->sparse_mem_base && size <= 7 * 16*MB) {
			if (((start / (16*MB)) & 0x7) == 0) {
				start &= ~(128*MB - 1);
				start += 16*MB;
				start  = ALIGN(start, alignto);
			}
			if (start/(128*MB) != (start + size - 1)/(128*MB)) {
				start &= ~(128*MB - 1);
				start += (128 + 16)*MB;
				start  = ALIGN(start, alignto);
			}
		}
	}

	return start;
}
#undef KB
#undef MB
#undef GB

static int __init
pcibios_init(void)
{
	if (alpha_mv.init_pci)
		alpha_mv.init_pci();
	return 0;
}

subsys_initcall(pcibios_init);

#ifdef ALPHA_RESTORE_SRM_SETUP
static struct pdev_srm_saved_conf *srm_saved_configs;

void pdev_save_srm_config(struct pci_dev *dev)
{
	struct pdev_srm_saved_conf *tmp;
	static int printed = 0;

	if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
		return;

	if (!printed) {
		printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
		printed = 1;
	}

	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
	if (!tmp) {
		printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
		return;
	}
	tmp->next = srm_saved_configs;
	tmp->dev = dev;

	pci_save_state(dev);

	srm_saved_configs = tmp;
}

void
pci_restore_srm_config(void)
{
	struct pdev_srm_saved_conf *tmp;

	/* No need to restore if probed only. */
	if (pci_has_flag(PCI_PROBE_ONLY))
		return;

	/* Restore SRM config. */
	for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
		pci_restore_state(tmp->dev);
	}
}
#endif

void pcibios_fixup_bus(struct pci_bus *bus)
{
	struct pci_dev *dev = bus->self;

	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
		pci_read_bridge_bases(bus);
	}

	list_for_each_entry(dev, &bus->devices, bus_list) {
		pdev_save_srm_config(dev);
	}
}

/*
 *  If we set up a device for bus mastering, we need to check the latency
 *  timer as certain firmware forgets to set it properly, as seen
 *  on SX164 and LX164 with SRM.
 */
void
pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat >= 16) return;
	printk("PCI: Setting latency timer of device %s to 64\n",
							pci_name(dev));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
}

void __init
pcibios_claim_one_bus(struct pci_bus *b)
{
	struct pci_dev *dev;
	struct pci_bus *child_bus;

	list_for_each_entry(dev, &b->devices, bus_list) {
		int i;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			struct resource *r = &dev->resource[i];

			if (r->parent || !r->start || !r->flags)
				continue;
			if (pci_has_flag(PCI_PROBE_ONLY) ||
			    (r->flags & IORESOURCE_PCI_FIXED)) {
				if (pci_claim_resource(dev, i) == 0)
					continue;

				pci_claim_bridge_resource(dev, i);
			}
		}
	}

	list_for_each_entry(child_bus, &b->children, node)
		pcibios_claim_one_bus(child_bus);
}

static void __init
pcibios_claim_console_setup(void)
{
	struct pci_bus *b;

	list_for_each_entry(b, &pci_root_buses, node)
		pcibios_claim_one_bus(b);
}

void __init
common_init_pci(void)
{
	struct pci_controller *hose;
	struct list_head resources;
	struct pci_host_bridge *bridge;
	struct pci_bus *bus;
	int ret, next_busno;
	int need_domain_info = 0;
	u32 pci_mem_end;
	u32 sg_base;
	unsigned long end;

	/* Scan all of the recorded PCI controllers.  */
	for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
		sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;

		/* Adjust hose mem_space limit to prevent PCI allocations
		   in the iommu windows. */
		pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
		end = hose->mem_space->start + pci_mem_end;
		if (hose->mem_space->end > end)
			hose->mem_space->end = end;

		INIT_LIST_HEAD(&resources);
		pci_add_resource_offset(&resources, hose->io_space,
					hose->io_space->start);
		pci_add_resource_offset(&resources, hose->mem_space,
					hose->mem_space->start);

		bridge = pci_alloc_host_bridge(0);
		if (!bridge)
			continue;

		list_splice_init(&resources, &bridge->windows);
		bridge->dev.parent = NULL;
		bridge->sysdata = hose;
		bridge->busnr = next_busno;
		bridge->ops = alpha_mv.pci_ops;
		bridge->swizzle_irq = alpha_mv.pci_swizzle;
		bridge->map_irq = alpha_mv.pci_map_irq;

		ret = pci_scan_root_bus_bridge(bridge);
		if (ret) {
			pci_free_host_bridge(bridge);
			continue;
		}

		bus = hose->bus = bridge->bus;
		hose->need_domain_info = need_domain_info;
		next_busno = bus->busn_res.end + 1;
		/* Don't allow 8-bit bus number overflow inside the hose -
		   reserve some space for bridges. */ 
		if (next_busno > 224) {
			next_busno = 0;
			need_domain_info = 1;
		}
	}

	pcibios_claim_console_setup();

	pci_assign_unassigned_resources();
	for (hose = hose_head; hose; hose = hose->next) {
		bus = hose->bus;
		if (bus)
			pci_bus_add_devices(bus);
	}
}

struct pci_controller * __init
alloc_pci_controller(void)
{
	struct pci_controller *hose;

	hose = alloc_bootmem(sizeof(*hose));

	*hose_tail = hose;
	hose_tail = &hose->next;

	return hose;
}

struct resource * __init
alloc_resource(void)
{
	return alloc_bootmem(sizeof(struct resource));
}


/* Provide information on locations of various I/O regions in physical
   memory.  Do this on a per-card basis so that we choose the right hose.  */

asmlinkage long
sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
{
	struct pci_controller *hose;
	struct pci_dev *dev;

	/* from hose or from bus.devfn */
	if (which & IOBASE_FROM_HOSE) {
		for(hose = hose_head; hose; hose = hose->next) 
			if (hose->index == bus) break;
		if (!hose) return -ENODEV;
	} else {
		/* Special hook for ISA access.  */
		if (bus == 0 && dfn == 0) {
			hose = pci_isa_hose;
		} else {
			dev = pci_get_bus_and_slot(bus, dfn);
			if (!dev)
				return -ENODEV;
			hose = dev->sysdata;
			pci_dev_put(dev);
		}
	}

	switch (which & ~IOBASE_FROM_HOSE) {
	case IOBASE_HOSE:
		return hose->index;
	case IOBASE_SPARSE_MEM:
		return hose->sparse_mem_base;
	case IOBASE_DENSE_MEM:
		return hose->dense_mem_base;
	case IOBASE_SPARSE_IO:
		return hose->sparse_io_base;
	case IOBASE_DENSE_IO:
		return hose->dense_io_base;
	case IOBASE_ROOT_BUS:
		return hose->bus->number;
	}

	return -EOPNOTSUPP;
}

/* Destroy an __iomem token.  Not copied from lib/iomap.c.  */

void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
	if (__is_mmio(addr))
		iounmap(addr);
}

EXPORT_SYMBOL(pci_iounmap);

/* FIXME: Some boxes have multiple ISA bridges! */
struct pci_dev *isa_bridge;
EXPORT_SYMBOL(isa_bridge);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* linux/arch/alpha/kernel/pci.c
	4	*
	5	* Extruded from code written by
	6	* Dave Rusling (david.rusling@reo.mts.dec.com)
	7	* David Mosberger (davidm@cs.arizona.edu)
	8	*/
	9
	10	/* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
	11
	12	/*
	13	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	14	* PCI-PCI bridges cleanup
	15	*/
1da177e4 LT	16	#include <linux/string.h>
	17	#include <linux/pci.h>
	18	#include <linux/init.h>
	19	#include <linux/ioport.h>
	20	#include <linux/kernel.h>
	21	#include <linux/bootmem.h>
	22	#include <linux/module.h>
	23	#include <linux/cache.h>
	24	#include <linux/slab.h>
	25	#include <asm/machvec.h>
	26
	27	#include "proto.h"
	28	#include "pci_impl.h"
	29
	30
	31	/*
	32	* Some string constants used by the various core logics.
	33	*/
	34
	35	const char *const pci_io_names[] = {
	36	"PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
	37	"PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
	38	};
	39
	40	const char *const pci_mem_names[] = {
	41	"PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
	42	"PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
	43	};
	44
	45	const char pci_hae0_name[] = "HAE0";
	46
1da177e4	47	/*
151d16d5 BH	48	* If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
151d16d5 BH	49	* assignments.
1da177e4	50	*/
1da177e4 LT	51
	52	/*
	53	* The PCI controller list.
	54	*/
	55
	56	struct pci_controller hose_head, *hose_tail = &hose_head;
	57	struct pci_controller *pci_isa_hose;
	58
	59	/*
	60	* Quirks.
	61	*/
	62
f8d6c8d9	63	static void quirk_isa_bridge(struct pci_dev *dev)
1da177e4 LT	64	{
	65	dev->class = PCI_CLASS_BRIDGE_ISA << 8;
	66	}
	67	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
	68
f8d6c8d9	69	static void quirk_cypress(struct pci_dev *dev)
1da177e4	70	{
a744e016 IK	71	/* The Notorious Cy82C693 chip. */
	72
	73	/* The generic legacy mode IDE fixup in drivers/pci/probe.c
	74	doesn't work correctly with the Cypress IDE controller as
	75	it has non-standard register layout. Fix that. */
	76	if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
	77	dev->resource[2].start = dev->resource[3].start = 0;
	78	dev->resource[2].end = dev->resource[3].end = 0;
	79	dev->resource[2].flags = dev->resource[3].flags = 0;
	80	if (PCI_FUNC(dev->devfn) == 2) {
	81	dev->resource[0].start = 0x170;
	82	dev->resource[0].end = 0x177;
	83	dev->resource[1].start = 0x376;
	84	dev->resource[1].end = 0x376;
	85	}
	86	}
	87
1da177e4 LT	88	/* The Cypress bridge responds on the PCI bus in the address range
	89	0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
	90	way to turn this off. The bridge also supports several extended
	91	BIOS ranges (disabled after power-up), and some consoles do turn
	92	them on. So if we use a large direct-map window, or a large SG
	93	window, we must avoid the entire 0xfff00000-0xffffffff region. */
72cff123	94	if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
1da177e4 LT	95	if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
	96	__direct_map_size = 0xfff00000UL - __direct_map_base;
	97	else {
	98	struct pci_controller *hose = dev->sysdata;
	99	struct pci_iommu_arena *pci = hose->sg_pci;
	100	if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
	101	pci->size = 0xfff00000UL - pci->dma_base;
	102	}
	103	}
	104	}
	105	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
	106
	107	/* Called for each device after PCI setup is done. */
f8d6c8d9	108	static void pcibios_fixup_final(struct pci_dev *dev)
1da177e4 LT	109	{
	110	unsigned int class = dev->class >> 8;
	111
	112	if (class == PCI_CLASS_BRIDGE_ISA \|\| class == PCI_CLASS_BRIDGE_EISA) {
	113	dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
	114	isa_bridge = dev;
	115	}
	116	}
	117	DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
	118
	119	/* Just declaring that the power-of-ten prefixes are actually the
	120	power-of-two ones doesn't make it true :) */
	121	#define KB 1024
	122	#define MB (1024*KB)
	123	#define GB (1024*MB)
	124
b26b2d49	125	resource_size_t
3b7a17fc	126	pcibios_align_resource(void data, const struct resource res,
e31dd6e4	127	resource_size_t size, resource_size_t align)
1da177e4 LT	128	{
	129	struct pci_dev *dev = data;
	130	struct pci_controller *hose = dev->sysdata;
	131	unsigned long alignto;
e31dd6e4	132	resource_size_t start = res->start;
1da177e4 LT	133
	134	if (res->flags & IORESOURCE_IO) {
	135	/* Make sure we start at our min on all hoses */
	136	if (start - hose->io_space->start < PCIBIOS_MIN_IO)
	137	start = PCIBIOS_MIN_IO + hose->io_space->start;
	138
	139	/*
	140	* Put everything into 0x00-0xff region modulo 0x400
	141	*/
	142	if (start & 0x300)
	143	start = (start + 0x3ff) & ~0x3ff;
	144	}
	145	else if (res->flags & IORESOURCE_MEM) {
	146	/* Make sure we start at our min on all hoses */
	147	if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
	148	start = PCIBIOS_MIN_MEM + hose->mem_space->start;
	149
	150	/*
	151	* The following holds at least for the Low Cost
	152	* Alpha implementation of the PCI interface:
	153	*
	154	* In sparse memory address space, the first
	155	* octant (16MB) of every 128MB segment is
	156	* aliased to the very first 16 MB of the
	157	* address space (i.e., it aliases the ISA
	158	* memory address space). Thus, we try to
	159	* avoid allocating PCI devices in that range.
	160	* Can be allocated in 2nd-7th octant only.
	161	* Devices that need more than 112MB of
	162	* address space must be accessed through
	163	* dense memory space only!
	164	*/
	165
	166	/* Align to multiple of size of minimum base. */
5f0e3da6	167	alignto = max_t(resource_size_t, 0x1000, align);
1da177e4 LT	168	start = ALIGN(start, alignto);
	169	if (hose->sparse_mem_base && size <= 7 * 16*MB) {
	170	if (((start / (16*MB)) & 0x7) == 0) {
	171	start &= ~(128*MB - 1);
	172	start += 16*MB;
	173	start = ALIGN(start, alignto);
	174	}
	175	if (start/(128MB) != (start + size - 1)/(128MB)) {
	176	start &= ~(128*MB - 1);
	177	start += (128 + 16)*MB;
	178	start = ALIGN(start, alignto);
	179	}
	180	}
	181	}
	182
b26b2d49	183	return start;
1da177e4 LT	184	}
	185	#undef KB
	186	#undef MB
	187	#undef GB
	188
	189	static int __init
	190	pcibios_init(void)
	191	{
	192	if (alpha_mv.init_pci)
	193	alpha_mv.init_pci();
	194	return 0;
	195	}
	196
	197	subsys_initcall(pcibios_init);
	198
1da177e4 LT	199	#ifdef ALPHA_RESTORE_SRM_SETUP
	200	static struct pdev_srm_saved_conf *srm_saved_configs;
	201
f8d6c8d9	202	void pdev_save_srm_config(struct pci_dev *dev)
1da177e4 LT	203	{
	204	struct pdev_srm_saved_conf *tmp;
	205	static int printed = 0;
	206
151d16d5	207	if (!alpha_using_srm \|\| pci_has_flag(PCI_PROBE_ONLY))
1da177e4 LT	208	return;
	209
	210	if (!printed) {
	211	printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
	212	printed = 1;
	213	}
	214
	215	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
	216	if (!tmp) {
bbb8d343	217	printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
1da177e4 LT	218	return;
	219	}
	220	tmp->next = srm_saved_configs;
	221	tmp->dev = dev;
	222
	223	pci_save_state(dev);
	224
	225	srm_saved_configs = tmp;
	226	}
	227
	228	void
	229	pci_restore_srm_config(void)
	230	{
	231	struct pdev_srm_saved_conf *tmp;
	232
	233	/* No need to restore if probed only. */
151d16d5	234	if (pci_has_flag(PCI_PROBE_ONLY))
1da177e4 LT	235	return;
	236
	237	/* Restore SRM config. */
	238	for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
	239	pci_restore_state(tmp->dev);
	240	}
	241	}
	242	#endif
	243
f8d6c8d9	244	void pcibios_fixup_bus(struct pci_bus *bus)
1da177e4	245	{
237865f1 BH	246	struct pci_dev *dev = bus->self;
	247
	248	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
	249	(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
	250	pci_read_bridge_bases(bus);
	251	}
1da177e4 LT	252
	253	list_for_each_entry(dev, &bus->devices, bus_list) {
	254	pdev_save_srm_config(dev);
1da177e4 LT	255	}
	256	}
	257
1da177e4 LT	258	/*
	259	* If we set up a device for bus mastering, we need to check the latency
	260	* timer as certain firmware forgets to set it properly, as seen
	261	* on SX164 and LX164 with SRM.
	262	*/
	263	void
	264	pcibios_set_master(struct pci_dev *dev)
	265	{
	266	u8 lat;
	267	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	268	if (lat >= 16) return;
	269	printk("PCI: Setting latency timer of device %s to 64\n",
	270	pci_name(dev));
	271	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	272	}
	273
72cff123	274	void __init
1da177e4 LT	275	pcibios_claim_one_bus(struct pci_bus *b)
	276	{
	277	struct pci_dev *dev;
	278	struct pci_bus *child_bus;
	279
	280	list_for_each_entry(dev, &b->devices, bus_list) {
	281	int i;
	282
	283	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	284	struct resource *r = &dev->resource[i];
	285
	286	if (r->parent \|\| !r->start \|\| !r->flags)
	287	continue;
151d16d5	288	if (pci_has_flag(PCI_PROBE_ONLY) \|\|
b3e11822 YL	289	(r->flags & IORESOURCE_PCI_FIXED)) {
	290	if (pci_claim_resource(dev, i) == 0)
	291	continue;
	292
	293	pci_claim_bridge_resource(dev, i);
	294	}
1da177e4 LT	295	}
	296	}
	297
	298	list_for_each_entry(child_bus, &b->children, node)
	299	pcibios_claim_one_bus(child_bus);
	300	}
	301
	302	static void __init
	303	pcibios_claim_console_setup(void)
	304	{
	305	struct pci_bus *b;
	306
	307	list_for_each_entry(b, &pci_root_buses, node)
	308	pcibios_claim_one_bus(b);
	309	}
	310
	311	void __init
	312	common_init_pci(void)
	313	{
	314	struct pci_controller *hose;
a2f33da1	315	struct list_head resources;
0e4c2eeb	316	struct pci_host_bridge *bridge;
1da177e4	317	struct pci_bus *bus;
0e4c2eeb	318	int ret, next_busno;
1da177e4	319	int need_domain_info = 0;
a2f33da1 BH	320	u32 pci_mem_end;
	321	u32 sg_base;
	322	unsigned long end;
1da177e4 LT	323
	324	/* Scan all of the recorded PCI controllers. */
	325	for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
a2f33da1 BH	326	sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
	327
	328	/* Adjust hose mem_space limit to prevent PCI allocations
	329	in the iommu windows. */
	330	pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
	331	end = hose->mem_space->start + pci_mem_end;
	332	if (hose->mem_space->end > end)
	333	hose->mem_space->end = end;
	334
	335	INIT_LIST_HEAD(&resources);
c04d9e35 BH	336	pci_add_resource_offset(&resources, hose->io_space,
	337	hose->io_space->start);
	338	pci_add_resource_offset(&resources, hose->mem_space,
	339	hose->mem_space->start);
a2f33da1	340
0e4c2eeb LP	341	bridge = pci_alloc_host_bridge(0);
0e4c2eeb LP	342	if (!bridge)
b97ea289	343	continue;
0e4c2eeb LP	344
	345	list_splice_init(&resources, &bridge->windows);
	346	bridge->dev.parent = NULL;
	347	bridge->sysdata = hose;
	348	bridge->busnr = next_busno;
	349	bridge->ops = alpha_mv.pci_ops;
	350	bridge->swizzle_irq = alpha_mv.pci_swizzle;
	351	bridge->map_irq = alpha_mv.pci_map_irq;
	352
	353	ret = pci_scan_root_bus_bridge(bridge);
	354	if (ret) {
	355	pci_free_host_bridge(bridge);
	356	continue;
	357	}
	358
	359	bus = hose->bus = bridge->bus;
1da177e4	360	hose->need_domain_info = need_domain_info;
b918c62e	361	next_busno = bus->busn_res.end + 1;
1da177e4 LT	362	/* Don't allow 8-bit bus number overflow inside the hose -
	363	reserve some space for bridges. */
	364	if (next_busno > 224) {
	365	next_busno = 0;
	366	need_domain_info = 1;
	367	}
	368	}
	369
72cff123	370	pcibios_claim_console_setup();
1da177e4 LT	371
1da177e4 LT	372	pci_assign_unassigned_resources();
b97ea289 YW	373	for (hose = hose_head; hose; hose = hose->next) {
	374	bus = hose->bus;
	375	if (bus)
	376	pci_bus_add_devices(bus);
	377	}
1da177e4 LT	378	}
1da177e4 LT	379
1da177e4 LT	380	struct pci_controller * __init
	381	alloc_pci_controller(void)
	382	{
	383	struct pci_controller *hose;
	384
	385	hose = alloc_bootmem(sizeof(*hose));
	386
	387	*hose_tail = hose;
	388	hose_tail = &hose->next;
	389
	390	return hose;
	391	}
	392
	393	struct resource * __init
	394	alloc_resource(void)
	395	{
203308a5	396	return alloc_bootmem(sizeof(struct resource));
1da177e4 LT	397	}
	398
	399
	400	/* Provide information on locations of various I/O regions in physical
	401	memory. Do this on a per-card basis so that we choose the right hose. */
	402
	403	asmlinkage long
	404	sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
	405	{
	406	struct pci_controller *hose;
	407	struct pci_dev *dev;
	408
	409	/* from hose or from bus.devfn */
	410	if (which & IOBASE_FROM_HOSE) {
	411	for(hose = hose_head; hose; hose = hose->next)
	412	if (hose->index == bus) break;
	413	if (!hose) return -ENODEV;
	414	} else {
	415	/* Special hook for ISA access. */
	416	if (bus == 0 && dfn == 0) {
	417	hose = pci_isa_hose;
	418	} else {
074cec54	419	dev = pci_get_bus_and_slot(bus, dfn);
1da177e4 LT	420	if (!dev)
	421	return -ENODEV;
	422	hose = dev->sysdata;
074cec54	423	pci_dev_put(dev);
1da177e4 LT	424	}
	425	}
	426
	427	switch (which & ~IOBASE_FROM_HOSE) {
	428	case IOBASE_HOSE:
	429	return hose->index;
	430	case IOBASE_SPARSE_MEM:
	431	return hose->sparse_mem_base;
	432	case IOBASE_DENSE_MEM:
	433	return hose->dense_mem_base;
	434	case IOBASE_SPARSE_IO:
	435	return hose->sparse_io_base;
	436	case IOBASE_DENSE_IO:
	437	return hose->dense_io_base;
	438	case IOBASE_ROOT_BUS:
	439	return hose->bus->number;
	440	}
	441
	442	return -EOPNOTSUPP;
	443	}
	444
f2971c4c	445	/* Destroy an __iomem token. Not copied from lib/iomap.c. */
1da177e4 LT	446
	447	void pci_iounmap(struct pci_dev dev, void __iomem addr)
	448	{
	449	if (__is_mmio(addr))
	450	iounmap(addr);
	451	}
	452
1da177e4	453	EXPORT_SYMBOL(pci_iounmap);
8255cf35 AB	454
	455	/* FIXME: Some boxes have multiple ISA bridges! */
	456	struct pci_dev *isa_bridge;
	457	EXPORT_SYMBOL(isa_bridge);