[linux-2.6-block.git] / arch / alpha / kernel / pci.c

// SPDX-License-Identifier: GPL-2.0
/*
 *	linux/arch/alpha/kernel/pci.c
 *
 * Extruded from code written by
 *	Dave Rusling (david.rusling@reo.mts.dec.com)
 *	David Mosberger (davidm@cs.arizona.edu)
 */

/* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     PCI-PCI bridges cleanup
 */
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/memblock.h>
#include <linux/module.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include <linux/syscalls.h>
#include <asm/machvec.h>

#include "proto.h"
#include "pci_impl.h"


/*
 * Some string constants used by the various core logics. 
 */

const char *const pci_io_names[] = {
  "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
  "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
};

const char *const pci_mem_names[] = {
  "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
  "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
};

const char pci_hae0_name[] = "HAE0";

/*
 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
 * assignments.
 */

/*
 * The PCI controller list.
 */

struct pci_controller *hose_head, **hose_tail = &hose_head;
struct pci_controller *pci_isa_hose;

/*
 * Quirks.
 */

static void quirk_isa_bridge(struct pci_dev *dev)
{
	dev->class = PCI_CLASS_BRIDGE_ISA << 8;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);

static void quirk_cypress(struct pci_dev *dev)
{
	/* The Notorious Cy82C693 chip.  */

	/* The generic legacy mode IDE fixup in drivers/pci/probe.c
	   doesn't work correctly with the Cypress IDE controller as
	   it has non-standard register layout.  Fix that.  */
	if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
		dev->resource[2].start = dev->resource[3].start = 0;
		dev->resource[2].end = dev->resource[3].end = 0;
		dev->resource[2].flags = dev->resource[3].flags = 0;
		if (PCI_FUNC(dev->devfn) == 2) {
			dev->resource[0].start = 0x170;
			dev->resource[0].end = 0x177;
			dev->resource[1].start = 0x376;
			dev->resource[1].end = 0x376;
		}
	}

	/* The Cypress bridge responds on the PCI bus in the address range
	   0xffff0000-0xffffffff (conventional x86 BIOS ROM).  There is no
	   way to turn this off.  The bridge also supports several extended
	   BIOS ranges (disabled after power-up), and some consoles do turn
	   them on.  So if we use a large direct-map window, or a large SG
	   window, we must avoid the entire 0xfff00000-0xffffffff region.  */
	if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
		if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
			__direct_map_size = 0xfff00000UL - __direct_map_base;
		else {
			struct pci_controller *hose = dev->sysdata;
			struct pci_iommu_arena *pci = hose->sg_pci;
			if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
				pci->size = 0xfff00000UL - pci->dma_base;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);

/* Called for each device after PCI setup is done. */
static void pcibios_fixup_final(struct pci_dev *dev)
{
	unsigned int class = dev->class >> 8;

	if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
		dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
		isa_bridge = dev;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);

/* Just declaring that the power-of-ten prefixes are actually the
   power-of-two ones doesn't make it true :) */
#define KB			1024
#define MB			(1024*KB)
#define GB			(1024*MB)

resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
		       resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_controller *hose = dev->sysdata;
	unsigned long alignto;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		/* Make sure we start at our min on all hoses */
		if (start - hose->io_space->start < PCIBIOS_MIN_IO)
			start = PCIBIOS_MIN_IO + hose->io_space->start;

		/*
		 * Put everything into 0x00-0xff region modulo 0x400
		 */
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	}
	else if	(res->flags & IORESOURCE_MEM) {
		/* Make sure we start at our min on all hoses */
		if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
			start = PCIBIOS_MIN_MEM + hose->mem_space->start;

		/*
		 * The following holds at least for the Low Cost
		 * Alpha implementation of the PCI interface:
		 *
		 * In sparse memory address space, the first
		 * octant (16MB) of every 128MB segment is
		 * aliased to the very first 16 MB of the
		 * address space (i.e., it aliases the ISA
		 * memory address space).  Thus, we try to
		 * avoid allocating PCI devices in that range.
		 * Can be allocated in 2nd-7th octant only.
		 * Devices that need more than 112MB of
		 * address space must be accessed through
		 * dense memory space only!
		 */

		/* Align to multiple of size of minimum base.  */
		alignto = max_t(resource_size_t, 0x1000, align);
		start = ALIGN(start, alignto);
		if (hose->sparse_mem_base && size <= 7 * 16*MB) {
			if (((start / (16*MB)) & 0x7) == 0) {
				start &= ~(128*MB - 1);
				start += 16*MB;
				start  = ALIGN(start, alignto);
			}
			if (start/(128*MB) != (start + size - 1)/(128*MB)) {
				start &= ~(128*MB - 1);
				start += (128 + 16)*MB;
				start  = ALIGN(start, alignto);
			}
		}
	}

	return start;
}
#undef KB
#undef MB
#undef GB

static int __init
pcibios_init(void)
{
	if (alpha_mv.init_pci)
		alpha_mv.init_pci();
	return 0;
}

subsys_initcall(pcibios_init);

#ifdef ALPHA_RESTORE_SRM_SETUP
/* Store PCI device configuration left by SRM here. */
struct pdev_srm_saved_conf
{
	struct pdev_srm_saved_conf *next;
	struct pci_dev *dev;
};

static struct pdev_srm_saved_conf *srm_saved_configs;

static void pdev_save_srm_config(struct pci_dev *dev)
{
	struct pdev_srm_saved_conf *tmp;
	static int printed = 0;

	if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
		return;

	if (!printed) {
		printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
		printed = 1;
	}

	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
	if (!tmp) {
		printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
		return;
	}
	tmp->next = srm_saved_configs;
	tmp->dev = dev;

	pci_save_state(dev);

	srm_saved_configs = tmp;
}

void
pci_restore_srm_config(void)
{
	struct pdev_srm_saved_conf *tmp;

	/* No need to restore if probed only. */
	if (pci_has_flag(PCI_PROBE_ONLY))
		return;

	/* Restore SRM config. */
	for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
		pci_restore_state(tmp->dev);
	}
}
#else
#define pdev_save_srm_config(dev)	do {} while (0)
#endif

void pcibios_fixup_bus(struct pci_bus *bus)
{
	struct pci_dev *dev = bus->self;

	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
		pci_read_bridge_bases(bus);
	}

	list_for_each_entry(dev, &bus->devices, bus_list) {
		pdev_save_srm_config(dev);
	}
}

/*
 *  If we set up a device for bus mastering, we need to check the latency
 *  timer as certain firmware forgets to set it properly, as seen
 *  on SX164 and LX164 with SRM.
 */
void
pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat >= 16) return;
	printk("PCI: Setting latency timer of device %s to 64\n",
							pci_name(dev));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
}

void __init
pcibios_claim_one_bus(struct pci_bus *b)
{
	struct pci_dev *dev;
	struct pci_bus *child_bus;

	list_for_each_entry(dev, &b->devices, bus_list) {
		int i;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			struct resource *r = &dev->resource[i];

			if (r->parent || !r->start || !r->flags)
				continue;
			if (pci_has_flag(PCI_PROBE_ONLY) ||
			    (r->flags & IORESOURCE_PCI_FIXED)) {
				if (pci_claim_resource(dev, i) == 0)
					continue;

				pci_claim_bridge_resource(dev, i);
			}
		}
	}

	list_for_each_entry(child_bus, &b->children, node)
		pcibios_claim_one_bus(child_bus);
}

static void __init
pcibios_claim_console_setup(void)
{
	struct pci_bus *b;

	list_for_each_entry(b, &pci_root_buses, node)
		pcibios_claim_one_bus(b);
}

void __init
common_init_pci(void)
{
	struct pci_controller *hose;
	struct list_head resources;
	struct pci_host_bridge *bridge;
	struct pci_bus *bus;
	int ret, next_busno;
	int need_domain_info = 0;
	u32 pci_mem_end;
	u32 sg_base;
	unsigned long end;

	/* Scan all of the recorded PCI controllers.  */
	for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
		sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;

		/* Adjust hose mem_space limit to prevent PCI allocations
		   in the iommu windows. */
		pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
		end = hose->mem_space->start + pci_mem_end;
		if (hose->mem_space->end > end)
			hose->mem_space->end = end;

		INIT_LIST_HEAD(&resources);
		pci_add_resource_offset(&resources, hose->io_space,
					hose->io_space->start);
		pci_add_resource_offset(&resources, hose->mem_space,
					hose->mem_space->start);

		bridge = pci_alloc_host_bridge(0);
		if (!bridge)
			continue;

		list_splice_init(&resources, &bridge->windows);
		bridge->dev.parent = NULL;
		bridge->sysdata = hose;
		bridge->busnr = next_busno;
		bridge->ops = alpha_mv.pci_ops;
		bridge->swizzle_irq = alpha_mv.pci_swizzle;
		bridge->map_irq = alpha_mv.pci_map_irq;

		ret = pci_scan_root_bus_bridge(bridge);
		if (ret) {
			pci_free_host_bridge(bridge);
			continue;
		}

		bus = hose->bus = bridge->bus;
		hose->need_domain_info = need_domain_info;
		next_busno = bus->busn_res.end + 1;
		/* Don't allow 8-bit bus number overflow inside the hose -
		   reserve some space for bridges. */ 
		if (next_busno > 224) {
			next_busno = 0;
			need_domain_info = 1;
		}
	}

	pcibios_claim_console_setup();

	pci_assign_unassigned_resources();
	for (hose = hose_head; hose; hose = hose->next) {
		bus = hose->bus;
		if (bus)
			pci_bus_add_devices(bus);
	}
}

struct pci_controller * __init
alloc_pci_controller(void)
{
	struct pci_controller *hose;

	hose = memblock_alloc(sizeof(*hose), SMP_CACHE_BYTES);

	*hose_tail = hose;
	hose_tail = &hose->next;

	return hose;
}

struct resource * __init
alloc_resource(void)
{
	return memblock_alloc(sizeof(struct resource), SMP_CACHE_BYTES);
}


/* Provide information on locations of various I/O regions in physical
   memory.  Do this on a per-card basis so that we choose the right hose.  */

SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, bus,
		unsigned long, dfn)
{
	struct pci_controller *hose;
	struct pci_dev *dev;

	/* from hose or from bus.devfn */
	if (which & IOBASE_FROM_HOSE) {
		for(hose = hose_head; hose; hose = hose->next) 
			if (hose->index == bus) break;
		if (!hose) return -ENODEV;
	} else {
		/* Special hook for ISA access.  */
		if (bus == 0 && dfn == 0) {
			hose = pci_isa_hose;
		} else {
			dev = pci_get_domain_bus_and_slot(0, bus, dfn);
			if (!dev)
				return -ENODEV;
			hose = dev->sysdata;
			pci_dev_put(dev);
		}
	}

	switch (which & ~IOBASE_FROM_HOSE) {
	case IOBASE_HOSE:
		return hose->index;
	case IOBASE_SPARSE_MEM:
		return hose->sparse_mem_base;
	case IOBASE_DENSE_MEM:
		return hose->dense_mem_base;
	case IOBASE_SPARSE_IO:
		return hose->sparse_io_base;
	case IOBASE_DENSE_IO:
		return hose->dense_io_base;
	case IOBASE_ROOT_BUS:
		return hose->bus->number;
	}

	return -EOPNOTSUPP;
}

/* Destroy an __iomem token.  Not copied from lib/iomap.c.  */

void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
	if (__is_mmio(addr))
		iounmap(addr);
}

EXPORT_SYMBOL(pci_iounmap);

/* FIXME: Some boxes have multiple ISA bridges! */
struct pci_dev *isa_bridge;
EXPORT_SYMBOL(isa_bridge);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* linux/arch/alpha/kernel/pci.c
	4	*
	5	* Extruded from code written by
	6	* Dave Rusling (david.rusling@reo.mts.dec.com)
	7	* David Mosberger (davidm@cs.arizona.edu)
	8	*/
	9
	10	/* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
	11
	12	/*
	13	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	14	* PCI-PCI bridges cleanup
	15	*/
1da177e4 LT	16	#include <linux/string.h>
	17	#include <linux/pci.h>
	18	#include <linux/init.h>
	19	#include <linux/ioport.h>
	20	#include <linux/kernel.h>
57c8a661	21	#include <linux/memblock.h>
1da177e4 LT	22	#include <linux/module.h>
	23	#include <linux/cache.h>
	24	#include <linux/slab.h>
e4eacd6b	25	#include <linux/syscalls.h>
1da177e4 LT	26	#include <asm/machvec.h>
	27
	28	#include "proto.h"
	29	#include "pci_impl.h"
	30
	31
	32	/*
	33	* Some string constants used by the various core logics.
	34	*/
	35
	36	const char *const pci_io_names[] = {
	37	"PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
	38	"PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
	39	};
	40
	41	const char *const pci_mem_names[] = {
	42	"PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
	43	"PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
	44	};
	45
	46	const char pci_hae0_name[] = "HAE0";
	47
1da177e4	48	/*
151d16d5 BH	49	* If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
151d16d5 BH	50	* assignments.
1da177e4	51	*/
1da177e4 LT	52
	53	/*
	54	* The PCI controller list.
	55	*/
	56
	57	struct pci_controller hose_head, *hose_tail = &hose_head;
	58	struct pci_controller *pci_isa_hose;
	59
	60	/*
	61	* Quirks.
	62	*/
	63
f8d6c8d9	64	static void quirk_isa_bridge(struct pci_dev *dev)
1da177e4 LT	65	{
	66	dev->class = PCI_CLASS_BRIDGE_ISA << 8;
	67	}
	68	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
	69
f8d6c8d9	70	static void quirk_cypress(struct pci_dev *dev)
1da177e4	71	{
a744e016 IK	72	/* The Notorious Cy82C693 chip. */
	73
	74	/* The generic legacy mode IDE fixup in drivers/pci/probe.c
	75	doesn't work correctly with the Cypress IDE controller as
	76	it has non-standard register layout. Fix that. */
	77	if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
	78	dev->resource[2].start = dev->resource[3].start = 0;
	79	dev->resource[2].end = dev->resource[3].end = 0;
	80	dev->resource[2].flags = dev->resource[3].flags = 0;
	81	if (PCI_FUNC(dev->devfn) == 2) {
	82	dev->resource[0].start = 0x170;
	83	dev->resource[0].end = 0x177;
	84	dev->resource[1].start = 0x376;
	85	dev->resource[1].end = 0x376;
	86	}
	87	}
	88
1da177e4 LT	89	/* The Cypress bridge responds on the PCI bus in the address range
	90	0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
	91	way to turn this off. The bridge also supports several extended
	92	BIOS ranges (disabled after power-up), and some consoles do turn
	93	them on. So if we use a large direct-map window, or a large SG
	94	window, we must avoid the entire 0xfff00000-0xffffffff region. */
72cff123	95	if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
1da177e4 LT	96	if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
	97	__direct_map_size = 0xfff00000UL - __direct_map_base;
	98	else {
	99	struct pci_controller *hose = dev->sysdata;
	100	struct pci_iommu_arena *pci = hose->sg_pci;
	101	if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
	102	pci->size = 0xfff00000UL - pci->dma_base;
	103	}
	104	}
	105	}
	106	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
	107
	108	/* Called for each device after PCI setup is done. */
f8d6c8d9	109	static void pcibios_fixup_final(struct pci_dev *dev)
1da177e4 LT	110	{
	111	unsigned int class = dev->class >> 8;
	112
	113	if (class == PCI_CLASS_BRIDGE_ISA \|\| class == PCI_CLASS_BRIDGE_EISA) {
	114	dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
	115	isa_bridge = dev;
	116	}
	117	}
	118	DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
	119
	120	/* Just declaring that the power-of-ten prefixes are actually the
	121	power-of-two ones doesn't make it true :) */
	122	#define KB 1024
	123	#define MB (1024*KB)
	124	#define GB (1024*MB)
	125
b26b2d49	126	resource_size_t
3b7a17fc	127	pcibios_align_resource(void data, const struct resource res,
e31dd6e4	128	resource_size_t size, resource_size_t align)
1da177e4 LT	129	{
	130	struct pci_dev *dev = data;
	131	struct pci_controller *hose = dev->sysdata;
	132	unsigned long alignto;
e31dd6e4	133	resource_size_t start = res->start;
1da177e4 LT	134
	135	if (res->flags & IORESOURCE_IO) {
	136	/* Make sure we start at our min on all hoses */
	137	if (start - hose->io_space->start < PCIBIOS_MIN_IO)
	138	start = PCIBIOS_MIN_IO + hose->io_space->start;
	139
	140	/*
	141	* Put everything into 0x00-0xff region modulo 0x400
	142	*/
	143	if (start & 0x300)
	144	start = (start + 0x3ff) & ~0x3ff;
	145	}
	146	else if (res->flags & IORESOURCE_MEM) {
	147	/* Make sure we start at our min on all hoses */
	148	if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
	149	start = PCIBIOS_MIN_MEM + hose->mem_space->start;
	150
	151	/*
	152	* The following holds at least for the Low Cost
	153	* Alpha implementation of the PCI interface:
	154	*
	155	* In sparse memory address space, the first
	156	* octant (16MB) of every 128MB segment is
	157	* aliased to the very first 16 MB of the
	158	* address space (i.e., it aliases the ISA
	159	* memory address space). Thus, we try to
	160	* avoid allocating PCI devices in that range.
	161	* Can be allocated in 2nd-7th octant only.
	162	* Devices that need more than 112MB of
	163	* address space must be accessed through
	164	* dense memory space only!
	165	*/
	166
	167	/* Align to multiple of size of minimum base. */
5f0e3da6	168	alignto = max_t(resource_size_t, 0x1000, align);
1da177e4 LT	169	start = ALIGN(start, alignto);
	170	if (hose->sparse_mem_base && size <= 7 * 16*MB) {
	171	if (((start / (16*MB)) & 0x7) == 0) {
	172	start &= ~(128*MB - 1);
	173	start += 16*MB;
	174	start = ALIGN(start, alignto);
	175	}
	176	if (start/(128MB) != (start + size - 1)/(128MB)) {
	177	start &= ~(128*MB - 1);
	178	start += (128 + 16)*MB;
	179	start = ALIGN(start, alignto);
	180	}
	181	}
	182	}
	183
b26b2d49	184	return start;
1da177e4 LT	185	}
	186	#undef KB
	187	#undef MB
	188	#undef GB
	189
	190	static int __init
	191	pcibios_init(void)
	192	{
	193	if (alpha_mv.init_pci)
	194	alpha_mv.init_pci();
	195	return 0;
	196	}
	197
	198	subsys_initcall(pcibios_init);
	199
1da177e4	200	#ifdef ALPHA_RESTORE_SRM_SETUP
03f41f28 BH	201	/* Store PCI device configuration left by SRM here. */
	202	struct pdev_srm_saved_conf
	203	{
	204	struct pdev_srm_saved_conf *next;
	205	struct pci_dev *dev;
	206	};
	207
1da177e4 LT	208	static struct pdev_srm_saved_conf *srm_saved_configs;
1da177e4 LT	209
03f41f28	210	static void pdev_save_srm_config(struct pci_dev *dev)
1da177e4 LT	211	{
	212	struct pdev_srm_saved_conf *tmp;
	213	static int printed = 0;
	214
151d16d5	215	if (!alpha_using_srm \|\| pci_has_flag(PCI_PROBE_ONLY))
1da177e4 LT	216	return;
	217
	218	if (!printed) {
	219	printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
	220	printed = 1;
	221	}
	222
	223	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
	224	if (!tmp) {
bbb8d343	225	printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
1da177e4 LT	226	return;
	227	}
	228	tmp->next = srm_saved_configs;
	229	tmp->dev = dev;
	230
	231	pci_save_state(dev);
	232
	233	srm_saved_configs = tmp;
	234	}
	235
	236	void
	237	pci_restore_srm_config(void)
	238	{
	239	struct pdev_srm_saved_conf *tmp;
	240
	241	/* No need to restore if probed only. */
151d16d5	242	if (pci_has_flag(PCI_PROBE_ONLY))
1da177e4 LT	243	return;
	244
	245	/* Restore SRM config. */
	246	for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
	247	pci_restore_state(tmp->dev);
	248	}
	249	}
03f41f28 BH	250	#else
03f41f28 BH	251	#define pdev_save_srm_config(dev) do {} while (0)
1da177e4 LT	252	#endif
1da177e4 LT	253
f8d6c8d9	254	void pcibios_fixup_bus(struct pci_bus *bus)
1da177e4	255	{
237865f1 BH	256	struct pci_dev *dev = bus->self;
	257
	258	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
	259	(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
	260	pci_read_bridge_bases(bus);
	261	}
1da177e4 LT	262
	263	list_for_each_entry(dev, &bus->devices, bus_list) {
	264	pdev_save_srm_config(dev);
1da177e4 LT	265	}
	266	}
	267
1da177e4 LT	268	/*
	269	* If we set up a device for bus mastering, we need to check the latency
	270	* timer as certain firmware forgets to set it properly, as seen
	271	* on SX164 and LX164 with SRM.
	272	*/
	273	void
	274	pcibios_set_master(struct pci_dev *dev)
	275	{
	276	u8 lat;
	277	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	278	if (lat >= 16) return;
	279	printk("PCI: Setting latency timer of device %s to 64\n",
	280	pci_name(dev));
	281	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	282	}
	283
72cff123	284	void __init
1da177e4 LT	285	pcibios_claim_one_bus(struct pci_bus *b)
	286	{
	287	struct pci_dev *dev;
	288	struct pci_bus *child_bus;
	289
	290	list_for_each_entry(dev, &b->devices, bus_list) {
	291	int i;
	292
	293	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	294	struct resource *r = &dev->resource[i];
	295
	296	if (r->parent \|\| !r->start \|\| !r->flags)
	297	continue;
151d16d5	298	if (pci_has_flag(PCI_PROBE_ONLY) \|\|
b3e11822 YL	299	(r->flags & IORESOURCE_PCI_FIXED)) {
	300	if (pci_claim_resource(dev, i) == 0)
	301	continue;
	302
	303	pci_claim_bridge_resource(dev, i);
	304	}
1da177e4 LT	305	}
	306	}
	307
	308	list_for_each_entry(child_bus, &b->children, node)
	309	pcibios_claim_one_bus(child_bus);
	310	}
	311
	312	static void __init
	313	pcibios_claim_console_setup(void)
	314	{
	315	struct pci_bus *b;
	316
	317	list_for_each_entry(b, &pci_root_buses, node)
	318	pcibios_claim_one_bus(b);
	319	}
	320
	321	void __init
	322	common_init_pci(void)
	323	{
	324	struct pci_controller *hose;
a2f33da1	325	struct list_head resources;
0e4c2eeb	326	struct pci_host_bridge *bridge;
1da177e4	327	struct pci_bus *bus;
0e4c2eeb	328	int ret, next_busno;
1da177e4	329	int need_domain_info = 0;
a2f33da1 BH	330	u32 pci_mem_end;
	331	u32 sg_base;
	332	unsigned long end;
1da177e4 LT	333
	334	/* Scan all of the recorded PCI controllers. */
	335	for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
a2f33da1 BH	336	sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
	337
	338	/* Adjust hose mem_space limit to prevent PCI allocations
	339	in the iommu windows. */
	340	pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
	341	end = hose->mem_space->start + pci_mem_end;
	342	if (hose->mem_space->end > end)
	343	hose->mem_space->end = end;
	344
	345	INIT_LIST_HEAD(&resources);
c04d9e35 BH	346	pci_add_resource_offset(&resources, hose->io_space,
	347	hose->io_space->start);
	348	pci_add_resource_offset(&resources, hose->mem_space,
	349	hose->mem_space->start);
a2f33da1	350
0e4c2eeb LP	351	bridge = pci_alloc_host_bridge(0);
0e4c2eeb LP	352	if (!bridge)
b97ea289	353	continue;
0e4c2eeb LP	354
	355	list_splice_init(&resources, &bridge->windows);
	356	bridge->dev.parent = NULL;
	357	bridge->sysdata = hose;
	358	bridge->busnr = next_busno;
	359	bridge->ops = alpha_mv.pci_ops;
	360	bridge->swizzle_irq = alpha_mv.pci_swizzle;
	361	bridge->map_irq = alpha_mv.pci_map_irq;
	362
	363	ret = pci_scan_root_bus_bridge(bridge);
	364	if (ret) {
	365	pci_free_host_bridge(bridge);
	366	continue;
	367	}
	368
	369	bus = hose->bus = bridge->bus;
1da177e4	370	hose->need_domain_info = need_domain_info;
b918c62e	371	next_busno = bus->busn_res.end + 1;
1da177e4 LT	372	/* Don't allow 8-bit bus number overflow inside the hose -
	373	reserve some space for bridges. */
	374	if (next_busno > 224) {
	375	next_busno = 0;
	376	need_domain_info = 1;
	377	}
	378	}
	379
72cff123	380	pcibios_claim_console_setup();
1da177e4 LT	381
1da177e4 LT	382	pci_assign_unassigned_resources();
b97ea289 YW	383	for (hose = hose_head; hose; hose = hose->next) {
	384	bus = hose->bus;
	385	if (bus)
	386	pci_bus_add_devices(bus);
	387	}
1da177e4 LT	388	}
1da177e4 LT	389
1da177e4 LT	390	struct pci_controller * __init
	391	alloc_pci_controller(void)
	392	{
	393	struct pci_controller *hose;
	394
7e1c4e27	395	hose = memblock_alloc(sizeof(*hose), SMP_CACHE_BYTES);
1da177e4 LT	396
	397	*hose_tail = hose;
	398	hose_tail = &hose->next;
	399
	400	return hose;
	401	}
	402
	403	struct resource * __init
	404	alloc_resource(void)
	405	{
7e1c4e27	406	return memblock_alloc(sizeof(struct resource), SMP_CACHE_BYTES);
1da177e4 LT	407	}
	408
	409
	410	/* Provide information on locations of various I/O regions in physical
	411	memory. Do this on a per-card basis so that we choose the right hose. */
	412
e4eacd6b AV	413	SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, bus,
e4eacd6b AV	414	unsigned long, dfn)
1da177e4 LT	415	{
	416	struct pci_controller *hose;
	417	struct pci_dev *dev;
	418
	419	/* from hose or from bus.devfn */
	420	if (which & IOBASE_FROM_HOSE) {
	421	for(hose = hose_head; hose; hose = hose->next)
	422	if (hose->index == bus) break;
	423	if (!hose) return -ENODEV;
	424	} else {
	425	/* Special hook for ISA access. */
	426	if (bus == 0 && dfn == 0) {
	427	hose = pci_isa_hose;
	428	} else {
797cfc4f	429	dev = pci_get_domain_bus_and_slot(0, bus, dfn);
1da177e4 LT	430	if (!dev)
	431	return -ENODEV;
	432	hose = dev->sysdata;
074cec54	433	pci_dev_put(dev);
1da177e4 LT	434	}
	435	}
	436
	437	switch (which & ~IOBASE_FROM_HOSE) {
	438	case IOBASE_HOSE:
	439	return hose->index;
	440	case IOBASE_SPARSE_MEM:
	441	return hose->sparse_mem_base;
	442	case IOBASE_DENSE_MEM:
	443	return hose->dense_mem_base;
	444	case IOBASE_SPARSE_IO:
	445	return hose->sparse_io_base;
	446	case IOBASE_DENSE_IO:
	447	return hose->dense_io_base;
	448	case IOBASE_ROOT_BUS:
	449	return hose->bus->number;
	450	}
	451
	452	return -EOPNOTSUPP;
	453	}
	454
f2971c4c	455	/* Destroy an __iomem token. Not copied from lib/iomap.c. */
1da177e4 LT	456
	457	void pci_iounmap(struct pci_dev dev, void __iomem addr)
	458	{
	459	if (__is_mmio(addr))
	460	iounmap(addr);
	461	}
	462
1da177e4	463	EXPORT_SYMBOL(pci_iounmap);
8255cf35 AB	464
	465	/* FIXME: Some boxes have multiple ISA bridges! */
	466	struct pci_dev *isa_bridge;
	467	EXPORT_SYMBOL(isa_bridge);