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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * linux/arch/alpha/kernel/core_tsunami.c | |
4 | * | |
5 | * Based on code written by David A. Rusling (david.rusling@reo.mts.dec.com). | |
6 | * | |
7 | * Code common to all TSUNAMI core logic chips. | |
8 | */ | |
9 | ||
10 | #define __EXTERN_INLINE inline | |
11 | #include <asm/io.h> | |
12 | #include <asm/core_tsunami.h> | |
13 | #undef __EXTERN_INLINE | |
14 | ||
8fa19647 | 15 | #include <linux/module.h> |
1da177e4 LT |
16 | #include <linux/types.h> |
17 | #include <linux/pci.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/init.h> | |
57c8a661 | 20 | #include <linux/memblock.h> |
1da177e4 LT |
21 | |
22 | #include <asm/ptrace.h> | |
23 | #include <asm/smp.h> | |
025a2215 | 24 | #include <asm/vga.h> |
1da177e4 LT |
25 | |
26 | #include "proto.h" | |
27 | #include "pci_impl.h" | |
28 | ||
29 | /* Save Tsunami configuration data as the console had it set up. */ | |
30 | ||
31 | struct | |
32 | { | |
33 | unsigned long wsba[4]; | |
34 | unsigned long wsm[4]; | |
35 | unsigned long tba[4]; | |
36 | } saved_config[2] __attribute__((common)); | |
37 | ||
38 | /* | |
39 | * NOTE: Herein lie back-to-back mb instructions. They are magic. | |
40 | * One plausible explanation is that the I/O controller does not properly | |
41 | * handle the system transaction. Another involves timing. Ho hum. | |
42 | */ | |
43 | ||
44 | /* | |
45 | * BIOS32-style PCI interface: | |
46 | */ | |
47 | ||
48 | #define DEBUG_CONFIG 0 | |
49 | ||
50 | #if DEBUG_CONFIG | |
51 | # define DBG_CFG(args) printk args | |
52 | #else | |
53 | # define DBG_CFG(args) | |
54 | #endif | |
55 | ||
56 | ||
57 | /* | |
58 | * Given a bus, device, and function number, compute resulting | |
59 | * configuration space address | |
60 | * accordingly. It is therefore not safe to have concurrent | |
61 | * invocations to configuration space access routines, but there | |
62 | * really shouldn't be any need for this. | |
63 | * | |
64 | * Note that all config space accesses use Type 1 address format. | |
65 | * | |
66 | * Note also that type 1 is determined by non-zero bus number. | |
67 | * | |
68 | * Type 1: | |
69 | * | |
70 | * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 | |
71 | * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 | |
72 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | |
73 | * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| | |
74 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | |
75 | * | |
76 | * 31:24 reserved | |
77 | * 23:16 bus number (8 bits = 128 possible buses) | |
78 | * 15:11 Device number (5 bits) | |
79 | * 10:8 function number | |
80 | * 7:2 register number | |
81 | * | |
82 | * Notes: | |
83 | * The function number selects which function of a multi-function device | |
84 | * (e.g., SCSI and Ethernet). | |
85 | * | |
86 | * The register selects a DWORD (32 bit) register offset. Hence it | |
87 | * doesn't get shifted by 2 bits as we want to "drop" the bottom two | |
88 | * bits. | |
89 | */ | |
90 | ||
91 | static int | |
92 | mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where, | |
93 | unsigned long *pci_addr, unsigned char *type1) | |
94 | { | |
95 | struct pci_controller *hose = pbus->sysdata; | |
96 | unsigned long addr; | |
97 | u8 bus = pbus->number; | |
98 | ||
99 | DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, " | |
100 | "pci_addr=0x%p, type1=0x%p)\n", | |
101 | bus, device_fn, where, pci_addr, type1)); | |
102 | ||
103 | if (!pbus->parent) /* No parent means peer PCI bus. */ | |
104 | bus = 0; | |
105 | *type1 = (bus != 0); | |
106 | ||
107 | addr = (bus << 16) | (device_fn << 8) | where; | |
108 | addr |= hose->config_space_base; | |
109 | ||
110 | *pci_addr = addr; | |
111 | DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr)); | |
112 | return 0; | |
113 | } | |
114 | ||
115 | static int | |
116 | tsunami_read_config(struct pci_bus *bus, unsigned int devfn, int where, | |
117 | int size, u32 *value) | |
118 | { | |
119 | unsigned long addr; | |
120 | unsigned char type1; | |
121 | ||
122 | if (mk_conf_addr(bus, devfn, where, &addr, &type1)) | |
123 | return PCIBIOS_DEVICE_NOT_FOUND; | |
124 | ||
125 | switch (size) { | |
126 | case 1: | |
127 | *value = __kernel_ldbu(*(vucp)addr); | |
128 | break; | |
129 | case 2: | |
130 | *value = __kernel_ldwu(*(vusp)addr); | |
131 | break; | |
132 | case 4: | |
133 | *value = *(vuip)addr; | |
134 | break; | |
135 | } | |
136 | ||
137 | return PCIBIOS_SUCCESSFUL; | |
138 | } | |
139 | ||
140 | static int | |
141 | tsunami_write_config(struct pci_bus *bus, unsigned int devfn, int where, | |
142 | int size, u32 value) | |
143 | { | |
144 | unsigned long addr; | |
145 | unsigned char type1; | |
146 | ||
147 | if (mk_conf_addr(bus, devfn, where, &addr, &type1)) | |
148 | return PCIBIOS_DEVICE_NOT_FOUND; | |
149 | ||
150 | switch (size) { | |
151 | case 1: | |
152 | __kernel_stb(value, *(vucp)addr); | |
153 | mb(); | |
154 | __kernel_ldbu(*(vucp)addr); | |
155 | break; | |
156 | case 2: | |
157 | __kernel_stw(value, *(vusp)addr); | |
158 | mb(); | |
159 | __kernel_ldwu(*(vusp)addr); | |
160 | break; | |
161 | case 4: | |
162 | *(vuip)addr = value; | |
163 | mb(); | |
164 | *(vuip)addr; | |
165 | break; | |
166 | } | |
167 | ||
168 | return PCIBIOS_SUCCESSFUL; | |
169 | } | |
170 | ||
171 | struct pci_ops tsunami_pci_ops = | |
172 | { | |
173 | .read = tsunami_read_config, | |
174 | .write = tsunami_write_config, | |
175 | }; | |
176 | \f | |
177 | void | |
178 | tsunami_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) | |
179 | { | |
180 | tsunami_pchip *pchip = hose->index ? TSUNAMI_pchip1 : TSUNAMI_pchip0; | |
181 | volatile unsigned long *csr; | |
182 | unsigned long value; | |
183 | ||
184 | /* We can invalidate up to 8 tlb entries in a go. The flush | |
185 | matches against <31:16> in the pci address. */ | |
186 | csr = &pchip->tlbia.csr; | |
187 | if (((start ^ end) & 0xffff0000) == 0) | |
188 | csr = &pchip->tlbiv.csr; | |
189 | ||
190 | /* For TBIA, it doesn't matter what value we write. For TBI, | |
191 | it's the shifted tag bits. */ | |
192 | value = (start & 0xffff0000) >> 12; | |
193 | ||
194 | *csr = value; | |
195 | mb(); | |
196 | *csr; | |
197 | } | |
198 | \f | |
199 | #ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI | |
200 | static long __init | |
201 | tsunami_probe_read(volatile unsigned long *vaddr) | |
202 | { | |
203 | long dont_care, probe_result; | |
204 | int cpu = smp_processor_id(); | |
205 | int s = swpipl(IPL_MCHECK - 1); | |
206 | ||
207 | mcheck_taken(cpu) = 0; | |
208 | mcheck_expected(cpu) = 1; | |
209 | mb(); | |
210 | dont_care = *vaddr; | |
211 | draina(); | |
212 | mcheck_expected(cpu) = 0; | |
213 | probe_result = !mcheck_taken(cpu); | |
214 | mcheck_taken(cpu) = 0; | |
215 | setipl(s); | |
216 | ||
217 | printk("dont_care == 0x%lx\n", dont_care); | |
218 | ||
219 | return probe_result; | |
220 | } | |
221 | ||
222 | static long __init | |
223 | tsunami_probe_write(volatile unsigned long *vaddr) | |
224 | { | |
225 | long true_contents, probe_result = 1; | |
226 | ||
227 | TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ | |
228 | true_contents = *vaddr; | |
229 | *vaddr = 0; | |
230 | draina(); | |
231 | if (TSUNAMI_cchip->misc.csr & (1L << 28)) { | |
232 | int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; | |
233 | TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ | |
234 | probe_result = 0; | |
235 | printk("tsunami_probe_write: unit %d at 0x%016lx\n", source, | |
236 | (unsigned long)vaddr); | |
237 | } | |
238 | if (probe_result) | |
239 | *vaddr = true_contents; | |
240 | return probe_result; | |
241 | } | |
242 | #else | |
243 | #define tsunami_probe_read(ADDR) 1 | |
244 | #endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */ | |
245 | ||
1da177e4 LT |
246 | static void __init |
247 | tsunami_init_one_pchip(tsunami_pchip *pchip, int index) | |
248 | { | |
249 | struct pci_controller *hose; | |
250 | ||
251 | if (tsunami_probe_read(&pchip->pctl.csr) == 0) | |
252 | return; | |
253 | ||
254 | hose = alloc_pci_controller(); | |
255 | if (index == 0) | |
256 | pci_isa_hose = hose; | |
257 | hose->io_space = alloc_resource(); | |
258 | hose->mem_space = alloc_resource(); | |
259 | ||
260 | /* This is for userland consumption. For some reason, the 40-bit | |
261 | PIO bias that we use in the kernel through KSEG didn't work for | |
262 | the page table based user mappings. So make sure we get the | |
263 | 43-bit PIO bias. */ | |
264 | hose->sparse_mem_base = 0; | |
265 | hose->sparse_io_base = 0; | |
266 | hose->dense_mem_base | |
267 | = (TSUNAMI_MEM(index) & 0xffffffffffL) | 0x80000000000L; | |
268 | hose->dense_io_base | |
269 | = (TSUNAMI_IO(index) & 0xffffffffffL) | 0x80000000000L; | |
270 | ||
271 | hose->config_space_base = TSUNAMI_CONF(index); | |
272 | hose->index = index; | |
273 | ||
274 | hose->io_space->start = TSUNAMI_IO(index) - TSUNAMI_IO_BIAS; | |
275 | hose->io_space->end = hose->io_space->start + TSUNAMI_IO_SPACE - 1; | |
276 | hose->io_space->name = pci_io_names[index]; | |
277 | hose->io_space->flags = IORESOURCE_IO; | |
278 | ||
279 | hose->mem_space->start = TSUNAMI_MEM(index) - TSUNAMI_MEM_BIAS; | |
280 | hose->mem_space->end = hose->mem_space->start + 0xffffffff; | |
281 | hose->mem_space->name = pci_mem_names[index]; | |
282 | hose->mem_space->flags = IORESOURCE_MEM; | |
283 | ||
284 | if (request_resource(&ioport_resource, hose->io_space) < 0) | |
285 | printk(KERN_ERR "Failed to request IO on hose %d\n", index); | |
286 | if (request_resource(&iomem_resource, hose->mem_space) < 0) | |
287 | printk(KERN_ERR "Failed to request MEM on hose %d\n", index); | |
288 | ||
289 | /* | |
290 | * Save the existing PCI window translations. SRM will | |
291 | * need them when we go to reboot. | |
292 | */ | |
293 | ||
294 | saved_config[index].wsba[0] = pchip->wsba[0].csr; | |
295 | saved_config[index].wsm[0] = pchip->wsm[0].csr; | |
296 | saved_config[index].tba[0] = pchip->tba[0].csr; | |
297 | ||
298 | saved_config[index].wsba[1] = pchip->wsba[1].csr; | |
299 | saved_config[index].wsm[1] = pchip->wsm[1].csr; | |
300 | saved_config[index].tba[1] = pchip->tba[1].csr; | |
301 | ||
302 | saved_config[index].wsba[2] = pchip->wsba[2].csr; | |
303 | saved_config[index].wsm[2] = pchip->wsm[2].csr; | |
304 | saved_config[index].tba[2] = pchip->tba[2].csr; | |
305 | ||
306 | saved_config[index].wsba[3] = pchip->wsba[3].csr; | |
307 | saved_config[index].wsm[3] = pchip->wsm[3].csr; | |
308 | saved_config[index].tba[3] = pchip->tba[3].csr; | |
309 | ||
310 | /* | |
311 | * Set up the PCI to main memory translation windows. | |
312 | * | |
313 | * Note: Window 3 is scatter-gather only | |
314 | * | |
315 | * Window 0 is scatter-gather 8MB at 8MB (for isa) | |
316 | * Window 1 is scatter-gather (up to) 1GB at 1GB | |
317 | * Window 2 is direct access 2GB at 2GB | |
318 | * | |
319 | * NOTE: we need the align_entry settings for Acer devices on ES40, | |
320 | * specifically floppy and IDE when memory is larger than 2GB. | |
321 | */ | |
7e1c4e27 MR |
322 | hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, |
323 | SMP_CACHE_BYTES); | |
1da177e4 LT |
324 | /* Initially set for 4 PTEs, but will be overridden to 64K for ISA. */ |
325 | hose->sg_isa->align_entry = 4; | |
326 | ||
327 | hose->sg_pci = iommu_arena_new(hose, 0x40000000, | |
7e1c4e27 MR |
328 | size_for_memory(0x40000000), |
329 | SMP_CACHE_BYTES); | |
1da177e4 LT |
330 | hose->sg_pci->align_entry = 4; /* Tsunami caches 4 PTEs at a time */ |
331 | ||
332 | __direct_map_base = 0x80000000; | |
333 | __direct_map_size = 0x80000000; | |
334 | ||
335 | pchip->wsba[0].csr = hose->sg_isa->dma_base | 3; | |
336 | pchip->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000; | |
337 | pchip->tba[0].csr = virt_to_phys(hose->sg_isa->ptes); | |
338 | ||
339 | pchip->wsba[1].csr = hose->sg_pci->dma_base | 3; | |
340 | pchip->wsm[1].csr = (hose->sg_pci->size - 1) & 0xfff00000; | |
341 | pchip->tba[1].csr = virt_to_phys(hose->sg_pci->ptes); | |
342 | ||
343 | pchip->wsba[2].csr = 0x80000000 | 1; | |
344 | pchip->wsm[2].csr = (0x80000000 - 1) & 0xfff00000; | |
345 | pchip->tba[2].csr = 0; | |
346 | ||
347 | pchip->wsba[3].csr = 0; | |
348 | ||
349 | /* Enable the Monster Window to make DAC pci64 possible. */ | |
350 | pchip->pctl.csr |= pctl_m_mwin; | |
351 | ||
352 | tsunami_pci_tbi(hose, 0, -1); | |
353 | } | |
354 | ||
025a2215 JE |
355 | |
356 | void __iomem * | |
357 | tsunami_ioportmap(unsigned long addr) | |
358 | { | |
359 | FIXUP_IOADDR_VGA(addr); | |
360 | return (void __iomem *)(addr + TSUNAMI_IO_BIAS); | |
361 | } | |
362 | ||
363 | void __iomem * | |
364 | tsunami_ioremap(unsigned long addr, unsigned long size) | |
365 | { | |
366 | FIXUP_MEMADDR_VGA(addr); | |
367 | return (void __iomem *)(addr + TSUNAMI_MEM_BIAS); | |
368 | } | |
369 | ||
370 | #ifndef CONFIG_ALPHA_GENERIC | |
371 | EXPORT_SYMBOL(tsunami_ioportmap); | |
372 | EXPORT_SYMBOL(tsunami_ioremap); | |
373 | #endif | |
374 | ||
1da177e4 LT |
375 | void __init |
376 | tsunami_init_arch(void) | |
377 | { | |
378 | #ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI | |
379 | unsigned long tmp; | |
380 | ||
381 | /* Ho hum.. init_arch is called before init_IRQ, but we need to be | |
382 | able to handle machine checks. So install the handler now. */ | |
383 | wrent(entInt, 0); | |
384 | ||
385 | /* NXMs just don't matter to Tsunami--unless they make it | |
386 | choke completely. */ | |
387 | tmp = (unsigned long)(TSUNAMI_cchip - 1); | |
bbb8d343 | 388 | printk("%s: probing bogus address: 0x%016lx\n", __func__, bogus_addr); |
1da177e4 LT |
389 | printk("\tprobe %s\n", |
390 | tsunami_probe_write((unsigned long *)bogus_addr) | |
391 | ? "succeeded" : "failed"); | |
392 | #endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */ | |
393 | ||
394 | #if 0 | |
bbb8d343 HH |
395 | printk("%s: CChip registers:\n", __func__); |
396 | printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr); | |
397 | printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr); | |
398 | printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr); | |
399 | printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr); | |
400 | printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr); | |
401 | printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr); | |
402 | printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr); | |
403 | printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr); | |
1da177e4 LT |
404 | |
405 | printk("%s: DChip registers:\n"); | |
bbb8d343 HH |
406 | printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr); |
407 | printk("%s: CSR_STR 0x%lx\n", __func__, TSUNAMI_dchip->str.csr); | |
408 | printk("%s: CSR_DREV 0x%lx\n", __func__, TSUNAMI_dchip->drev.csr); | |
1da177e4 LT |
409 | #endif |
410 | /* With multiple PCI busses, we play with I/O as physical addrs. */ | |
411 | ioport_resource.end = ~0UL; | |
412 | ||
413 | /* Find how many hoses we have, and initialize them. TSUNAMI | |
414 | and TYPHOON can have 2, but might only have 1 (DS10). */ | |
415 | ||
416 | tsunami_init_one_pchip(TSUNAMI_pchip0, 0); | |
417 | if (TSUNAMI_cchip->csc.csr & 1L<<14) | |
418 | tsunami_init_one_pchip(TSUNAMI_pchip1, 1); | |
025a2215 JE |
419 | |
420 | /* Check for graphic console location (if any). */ | |
421 | find_console_vga_hose(); | |
1da177e4 LT |
422 | } |
423 | ||
424 | static void | |
425 | tsunami_kill_one_pchip(tsunami_pchip *pchip, int index) | |
426 | { | |
427 | pchip->wsba[0].csr = saved_config[index].wsba[0]; | |
428 | pchip->wsm[0].csr = saved_config[index].wsm[0]; | |
429 | pchip->tba[0].csr = saved_config[index].tba[0]; | |
430 | ||
431 | pchip->wsba[1].csr = saved_config[index].wsba[1]; | |
432 | pchip->wsm[1].csr = saved_config[index].wsm[1]; | |
433 | pchip->tba[1].csr = saved_config[index].tba[1]; | |
434 | ||
435 | pchip->wsba[2].csr = saved_config[index].wsba[2]; | |
436 | pchip->wsm[2].csr = saved_config[index].wsm[2]; | |
437 | pchip->tba[2].csr = saved_config[index].tba[2]; | |
438 | ||
439 | pchip->wsba[3].csr = saved_config[index].wsba[3]; | |
440 | pchip->wsm[3].csr = saved_config[index].wsm[3]; | |
441 | pchip->tba[3].csr = saved_config[index].tba[3]; | |
442 | } | |
443 | ||
444 | void | |
445 | tsunami_kill_arch(int mode) | |
446 | { | |
447 | tsunami_kill_one_pchip(TSUNAMI_pchip0, 0); | |
448 | if (TSUNAMI_cchip->csc.csr & 1L<<14) | |
449 | tsunami_kill_one_pchip(TSUNAMI_pchip1, 1); | |
450 | } | |
451 | ||
452 | static inline void | |
453 | tsunami_pci_clr_err_1(tsunami_pchip *pchip) | |
454 | { | |
455 | pchip->perror.csr; | |
456 | pchip->perror.csr = 0x040; | |
457 | mb(); | |
458 | pchip->perror.csr; | |
459 | } | |
460 | ||
461 | static inline void | |
462 | tsunami_pci_clr_err(void) | |
463 | { | |
464 | tsunami_pci_clr_err_1(TSUNAMI_pchip0); | |
465 | ||
466 | /* TSUNAMI and TYPHOON can have 2, but might only have 1 (DS10) */ | |
467 | if (TSUNAMI_cchip->csc.csr & 1L<<14) | |
468 | tsunami_pci_clr_err_1(TSUNAMI_pchip1); | |
469 | } | |
470 | ||
471 | void | |
4fa1970a | 472 | tsunami_machine_check(unsigned long vector, unsigned long la_ptr) |
1da177e4 LT |
473 | { |
474 | /* Clear error before any reporting. */ | |
475 | mb(); | |
476 | mb(); /* magic */ | |
477 | draina(); | |
478 | tsunami_pci_clr_err(); | |
479 | wrmces(0x7); | |
480 | mb(); | |
481 | ||
4fa1970a | 482 | process_mcheck_info(vector, la_ptr, "TSUNAMI", |
1da177e4 LT |
483 | mcheck_expected(smp_processor_id())); |
484 | } |