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9cdd273e | 1 | ============================== |
96de0e25 | 2 | PXA2xx SPI on SSP driver HOWTO |
9cdd273e MCC |
3 | ============================== |
4 | ||
f96e6c0e AS |
5 | This a mini HOWTO on the pxa2xx_spi driver. The driver turns a PXA2xx |
6 | synchronous serial port into an SPI master controller | |
9cdd273e | 7 | (see Documentation/spi/spi-summary.rst). The driver has the following features |
e0c9905e | 8 | |
f96e6c0e | 9 | - Support for any PXA2xx and compatible SSP. |
e0c9905e SS |
10 | - SSP PIO and SSP DMA data transfers. |
11 | - External and Internal (SSPFRM) chip selects. | |
12 | - Per slave device (chip) configuration. | |
13 | - Full suspend, freeze, resume support. | |
14 | ||
f96e6c0e AS |
15 | The driver is built around a &struct spi_message FIFO serviced by kernel |
16 | thread. The kernel thread, spi_pump_messages(), drives message FIFO and | |
17 | is responsible for queuing SPI transactions and setting up and launching | |
18 | the DMA or interrupt driven transfers. | |
e0c9905e SS |
19 | |
20 | Declaring PXA2xx Master Controllers | |
21 | ----------------------------------- | |
f96e6c0e AS |
22 | Typically, for a legacy platform, an SPI master is defined in the |
23 | arch/.../mach-*/board-*.c as a "platform device". The master configuration | |
24 | is passed to the driver via a table found in include/linux/spi/pxa2xx_spi.h:: | |
e0c9905e | 25 | |
9cdd273e | 26 | struct pxa2xx_spi_controller { |
e0c9905e SS |
27 | u16 num_chipselect; |
28 | u8 enable_dma; | |
f96e6c0e | 29 | ... |
9cdd273e | 30 | }; |
e0c9905e | 31 | |
51eea52d | 32 | The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of |
e0c9905e SS |
33 | slave device (chips) attached to this SPI master. |
34 | ||
51eea52d | 35 | The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should |
f96e6c0e AS |
36 | be used. This caused the driver to acquire two DMA channels: Rx channel and |
37 | Tx channel. The Rx channel has a higher DMA service priority than the Tx channel. | |
e0c9905e SS |
38 | See the "PXA2xx Developer Manual" section "DMA Controller". |
39 | ||
f96e6c0e AS |
40 | For the new platforms the description of the controller and peripheral devices |
41 | comes from Device Tree or ACPI. | |
42 | ||
e0c9905e SS |
43 | NSSP MASTER SAMPLE |
44 | ------------------ | |
f96e6c0e | 45 | Below is a sample configuration using the PXA255 NSSP for a legacy platform:: |
e0c9905e | 46 | |
9cdd273e | 47 | static struct resource pxa_spi_nssp_resources[] = { |
e0c9905e SS |
48 | [0] = { |
49 | .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */ | |
50 | .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */ | |
51 | .flags = IORESOURCE_MEM, | |
52 | }, | |
53 | [1] = { | |
54 | .start = IRQ_NSSP, /* NSSP IRQ */ | |
55 | .end = IRQ_NSSP, | |
56 | .flags = IORESOURCE_IRQ, | |
57 | }, | |
9cdd273e | 58 | }; |
e0c9905e | 59 | |
9cdd273e | 60 | static struct pxa2xx_spi_controller pxa_nssp_master_info = { |
e0c9905e SS |
61 | .num_chipselect = 1, /* Matches the number of chips attached to NSSP */ |
62 | .enable_dma = 1, /* Enables NSSP DMA */ | |
9cdd273e | 63 | }; |
e0c9905e | 64 | |
9cdd273e | 65 | static struct platform_device pxa_spi_nssp = { |
e0c9905e SS |
66 | .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */ |
67 | .id = 2, /* Bus number, MUST MATCH SSP number 1..n */ | |
68 | .resource = pxa_spi_nssp_resources, | |
69 | .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources), | |
70 | .dev = { | |
71 | .platform_data = &pxa_nssp_master_info, /* Passed to driver */ | |
72 | }, | |
9cdd273e | 73 | }; |
e0c9905e | 74 | |
9cdd273e | 75 | static struct platform_device *devices[] __initdata = { |
e0c9905e | 76 | &pxa_spi_nssp, |
9cdd273e | 77 | }; |
e0c9905e | 78 | |
9cdd273e MCC |
79 | static void __init board_init(void) |
80 | { | |
e0c9905e | 81 | (void)platform_add_device(devices, ARRAY_SIZE(devices)); |
9cdd273e | 82 | } |
e0c9905e SS |
83 | |
84 | Declaring Slave Devices | |
85 | ----------------------- | |
f96e6c0e AS |
86 | Typically, for a legacy platform, each SPI slave (chip) is defined in the |
87 | arch/.../mach-*/board-*.c using the "spi_board_info" structure found in | |
88 | "linux/spi/spi.h". See "Documentation/spi/spi-summary.rst" for additional | |
89 | information. | |
e0c9905e SS |
90 | |
91 | Each slave device attached to the PXA must provide slave specific configuration | |
92 | information via the structure "pxa2xx_spi_chip" found in | |
8348c259 | 93 | "include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi master controller driver |
e0c9905e | 94 | will uses the configuration whenever the driver communicates with the slave |
f1f640a9 | 95 | device. All fields are optional. |
e0c9905e | 96 | |
9cdd273e MCC |
97 | :: |
98 | ||
99 | struct pxa2xx_spi_chip { | |
e0c9905e SS |
100 | u8 tx_threshold; |
101 | u8 rx_threshold; | |
102 | u8 dma_burst_size; | |
8d94cc50 | 103 | u32 timeout; |
e0c9905e SS |
104 | u8 enable_loopback; |
105 | void (*cs_control)(u32 command); | |
9cdd273e | 106 | }; |
e0c9905e SS |
107 | |
108 | The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are | |
f96e6c0e | 109 | used to configure the SSP hardware FIFO. These fields are critical to the |
e0c9905e | 110 | performance of pxa2xx_spi driver and misconfiguration will result in rx |
f96e6c0e | 111 | FIFO overruns (especially in PIO mode transfers). Good default values are:: |
e0c9905e | 112 | |
f1f640a9 VS |
113 | .tx_threshold = 8, |
114 | .rx_threshold = 8, | |
115 | ||
116 | The range is 1 to 16 where zero indicates "use default". | |
e0c9905e SS |
117 | |
118 | The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA | |
119 | engine and is related the "spi_device.bits_per_word" field. Read and understand | |
120 | the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers | |
121 | to determine the correct value. An SSP configured for byte-wide transfers would | |
f1f640a9 VS |
122 | use a value of 8. The driver will determine a reasonable default if |
123 | dma_burst_size == 0. | |
e0c9905e | 124 | |
8d94cc50 | 125 | The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle |
f96e6c0e | 126 | trailing bytes in the SSP receiver FIFO. The correct value for this field is |
e0c9905e | 127 | dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific |
670e9f34 | 128 | slave device. Please note that the PXA2xx SSP 1 does not support trailing byte |
e0c9905e SS |
129 | timeouts and must busy-wait any trailing bytes. |
130 | ||
131 | The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting | |
132 | into internal loopback mode. In this mode the SSP controller internally | |
670e9f34 | 133 | connects the SSPTX pin to the SSPRX pin. This is useful for initial setup |
e0c9905e SS |
134 | testing. |
135 | ||
136 | The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific | |
137 | function for asserting/deasserting a slave device chip select. If the field is | |
138 | NULL, the pxa2xx_spi master controller driver assumes that the SSP port is | |
f96e6c0e | 139 | configured to use GPIO or SSPFRM instead. |
e0c9905e | 140 | |
f1f640a9 VS |
141 | NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the |
142 | chipselect is dropped after each spi_transfer. Most devices need chip select | |
f96e6c0e | 143 | asserted around the complete message. Use SSPFRM as a GPIO (through a descriptor) |
25985edc | 144 | to accommodate these chips. |
f1f640a9 VS |
145 | |
146 | ||
147 | NSSP SLAVE SAMPLE | |
e0c9905e | 148 | ----------------- |
f96e6c0e AS |
149 | For a legacy platform or in some other cases, the pxa2xx_spi_chip structure |
150 | is passed to the pxa2xx_spi driver in the "spi_board_info.controller_data" | |
151 | field. Below is a sample configuration using the PXA255 NSSP. | |
e0c9905e | 152 | |
9cdd273e MCC |
153 | :: |
154 | ||
155 | /* Chip Select control for the CS8415A SPI slave device */ | |
156 | static void cs8415a_cs_control(u32 command) | |
157 | { | |
e0c9905e SS |
158 | if (command & PXA2XX_CS_ASSERT) |
159 | GPCR(2) = GPIO_bit(2); | |
160 | else | |
161 | GPSR(2) = GPIO_bit(2); | |
9cdd273e | 162 | } |
e0c9905e | 163 | |
9cdd273e MCC |
164 | /* Chip Select control for the CS8405A SPI slave device */ |
165 | static void cs8405a_cs_control(u32 command) | |
166 | { | |
e0c9905e SS |
167 | if (command & PXA2XX_CS_ASSERT) |
168 | GPCR(3) = GPIO_bit(3); | |
169 | else | |
170 | GPSR(3) = GPIO_bit(3); | |
9cdd273e | 171 | } |
e0c9905e | 172 | |
9cdd273e | 173 | static struct pxa2xx_spi_chip cs8415a_chip_info = { |
8d94cc50 SS |
174 | .tx_threshold = 8, /* SSP hardward FIFO threshold */ |
175 | .rx_threshold = 8, /* SSP hardward FIFO threshold */ | |
e0c9905e | 176 | .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ |
8d94cc50 | 177 | .timeout = 235, /* See Intel documentation */ |
e0c9905e | 178 | .cs_control = cs8415a_cs_control, /* Use external chip select */ |
9cdd273e | 179 | }; |
e0c9905e | 180 | |
9cdd273e | 181 | static struct pxa2xx_spi_chip cs8405a_chip_info = { |
8d94cc50 SS |
182 | .tx_threshold = 8, /* SSP hardward FIFO threshold */ |
183 | .rx_threshold = 8, /* SSP hardward FIFO threshold */ | |
e0c9905e | 184 | .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ |
8d94cc50 | 185 | .timeout = 235, /* See Intel documentation */ |
e0c9905e | 186 | .cs_control = cs8405a_cs_control, /* Use external chip select */ |
9cdd273e | 187 | }; |
e0c9905e | 188 | |
9cdd273e | 189 | static struct spi_board_info streetracer_spi_board_info[] __initdata = { |
e0c9905e SS |
190 | { |
191 | .modalias = "cs8415a", /* Name of spi_driver for this device */ | |
192 | .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ | |
193 | .bus_num = 2, /* Framework bus number */ | |
194 | .chip_select = 0, /* Framework chip select */ | |
195 | .platform_data = NULL; /* No spi_driver specific config */ | |
196 | .controller_data = &cs8415a_chip_info, /* Master chip config */ | |
197 | .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ | |
198 | }, | |
199 | { | |
200 | .modalias = "cs8405a", /* Name of spi_driver for this device */ | |
201 | .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ | |
202 | .bus_num = 2, /* Framework bus number */ | |
203 | .chip_select = 1, /* Framework chip select */ | |
204 | .controller_data = &cs8405a_chip_info, /* Master chip config */ | |
205 | .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ | |
206 | }, | |
9cdd273e | 207 | }; |
e0c9905e | 208 | |
9cdd273e MCC |
209 | static void __init streetracer_init(void) |
210 | { | |
e0c9905e SS |
211 | spi_register_board_info(streetracer_spi_board_info, |
212 | ARRAY_SIZE(streetracer_spi_board_info)); | |
9cdd273e | 213 | } |
e0c9905e SS |
214 | |
215 | ||
216 | DMA and PIO I/O Support | |
217 | ----------------------- | |
f1f640a9 VS |
218 | The pxa2xx_spi driver supports both DMA and interrupt driven PIO message |
219 | transfers. The driver defaults to PIO mode and DMA transfers must be enabled | |
f96e6c0e AS |
220 | by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure. |
221 | For the newer platforms, that are known to support DMA, the driver will enable | |
222 | it automatically and try it first with a possible fallback to PIO. The DMA | |
f1f640a9 | 223 | mode supports both coherent and stream based DMA mappings. |
e0c9905e SS |
224 | |
225 | The following logic is used to determine the type of I/O to be used on | |
9cdd273e | 226 | a per "spi_transfer" basis:: |
e0c9905e | 227 | |
9cdd273e | 228 | if !enable_dma then |
e0c9905e SS |
229 | always use PIO transfers |
230 | ||
9cdd273e | 231 | if spi_message.len > 8191 then |
f1f640a9 VS |
232 | print "rate limited" warning |
233 | use PIO transfers | |
234 | ||
9cdd273e | 235 | if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then |
e0c9905e SS |
236 | use coherent DMA mode |
237 | ||
9cdd273e | 238 | if rx_buf and tx_buf are aligned on 8 byte boundary then |
e0c9905e SS |
239 | use streaming DMA mode |
240 | ||
9cdd273e | 241 | otherwise |
e0c9905e SS |
242 | use PIO transfer |
243 | ||
244 | THANKS TO | |
245 | --------- | |
e0c9905e | 246 | David Brownell and others for mentoring the development of this driver. |