[linux-2.6-block.git] / Documentation / sound / alsa / soc / clocking.txt

Audio Clocking
==============

This text describes the audio clocking terms in ASoC and digital audio in
general. Note: Audio clocking can be complex !


Master Clock
------------

Every audio subsystem is driven by a master clock (sometimes refered to as MCLK
or SYSCLK). This audio master clock can be derived from a number of sources
(e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
audio playback and capture sample rates.

Some master clocks (e.g. PLL's and CPU based clocks) are configuarble in that
their speed can be altered by software (depending on the system use and to save
power). Other master clocks are fixed at at set frequency (i.e. crystals).


DAI Clocks
----------
The Digital Audio Interface is usually driven by a Bit Clock (often referred to
as BCLK). This clock is used to drive the digital audio data across the link
between the codec and CPU.

The DAI also has a frame clock to signal the start of each audio frame. This
clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
runs at exactly the sample rate (LRC = Rate).

Bit Clock can be generated as follows:-

BCLK = MCLK / x

 or

BCLK = LRC * x

 or

BCLK = LRC * Channels * Word Size

This relationship depends on the codec or SoC CPU in particular. In general
it's best to configure BCLK to the lowest possible speed (depending on your
rate, number of channels and wordsize) to save on power.

It's also desireable to use the codec (if possible) to drive (or master) the
audio clocks as it's usually gives more accurate sample rates than the CPU.
Commit	Line	Data
eb1a6af3 LG	1	Audio Clocking
	2	==============
	3
	4	This text describes the audio clocking terms in ASoC and digital audio in
	5	general. Note: Audio clocking can be complex !
	6
	7
	8	Master Clock
	9	------------
	10
	11	Every audio subsystem is driven by a master clock (sometimes refered to as MCLK
	12	or SYSCLK). This audio master clock can be derived from a number of sources
	13	(e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
	14	audio playback and capture sample rates.
	15
	16	Some master clocks (e.g. PLL's and CPU based clocks) are configuarble in that
	17	their speed can be altered by software (depending on the system use and to save
	18	power). Other master clocks are fixed at at set frequency (i.e. crystals).
	19
	20
	21	DAI Clocks
	22	----------
	23	The Digital Audio Interface is usually driven by a Bit Clock (often referred to
	24	as BCLK). This clock is used to drive the digital audio data across the link
	25	between the codec and CPU.
	26
	27	The DAI also has a frame clock to signal the start of each audio frame. This
	28	clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
a71a468a	29	runs at exactly the sample rate (LRC = Rate).
eb1a6af3	30
a71a468a	31	Bit Clock can be generated as follows:-
eb1a6af3 LG	32
	33	BCLK = MCLK / x
	34
	35	or
	36
	37	BCLK = LRC * x
	38
a71a468a LG	39	or
	40
	41	BCLK = LRC * Channels * Word Size
	42
10b98527 LG	43	This relationship depends on the codec or SoC CPU in particular. In general
	44	it's best to configure BCLK to the lowest possible speed (depending on your
	45	rate, number of channels and wordsize) to save on power.
eb1a6af3	46
10b98527 LG	47	It's also desireable to use the codec (if possible) to drive (or master) the
10b98527 LG	48	audio clocks as it's usually gives more accurate sample rates than the CPU.
eb1a6af3	49
eb1a6af3	50
eb1a6af3	51