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1 | .. SPDX-License-Identifier: GPL-2.0 |
2 | ||
3 | ========================================== | |
4 | Notes on register bank usage in the kernel | |
5 | ========================================== | |
f1517494 PM |
6 | |
7 | Introduction | |
8 | ------------ | |
9 | ||
10 | The SH-3 and SH-4 CPU families traditionally include a single partial register | |
11 | bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families | |
12 | may have more full-featured banking or simply no such capabilities at all. | |
13 | ||
14 | SR.RB banking | |
15 | ------------- | |
16 | ||
17 | In the case of this type of banking, banked registers are mapped directly to | |
18 | r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc | |
19 | can still be used to reference the banked registers (as r0_bank ... r7_bank) | |
20 | when in the context of another bank. The developer must keep the SR.RB value | |
21 | in mind when writing code that utilizes these banked registers, for obvious | |
22 | reasons. Userspace is also not able to poke at the bank1 values, so these can | |
23 | be used rather effectively as scratch registers by the kernel. | |
24 | ||
25 | Presently the kernel uses several of these registers. | |
26 | ||
27 | - r0_bank, r1_bank (referenced as k0 and k1, used for scratch | |
28 | registers when doing exception handling). | |
781885fd | 29 | |
f1517494 | 30 | - r2_bank (used to track the EXPEVT/INTEVT code) |
781885fd | 31 | |
f1517494 PM |
32 | - Used by do_IRQ() and friends for doing irq mapping based off |
33 | of the interrupt exception vector jump table offset | |
781885fd | 34 | |
f1517494 | 35 | - r6_bank (global interrupt mask) |
781885fd | 36 | |
f1517494 PM |
37 | - The SR.IMASK interrupt handler makes use of this to set the |
38 | interrupt priority level (used by local_irq_enable()) | |
f1517494 | 39 | |
781885fd | 40 | - r7_bank (current) |