projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| d6310a3f KG |
1 | Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) |
| 2 | ============================================================= | |
| 3 | ||
| 4 | The ThunderX2 SoC PMU consists of independent, system-wide, per-socket | |
| 5 | PMUs such as the Level 3 Cache (L3C) and DDR4 Memory Controller (DMC). | |
| 6 | ||
| 7 | The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles. | |
| 8 | Events are counted for the default channel (i.e. channel 0) and prorated | |
| 9 | to the total number of channels/tiles. | |
| 10 | ||
| 11 | The DMC and L3C support up to 4 counters. Counters are independently | |
| 12 | programmable and can be started and stopped individually. Each counter | |
| 13 | can be set to a different event. Counters are 32-bit and do not support | |
| 14 | an overflow interrupt; they are read every 2 seconds. | |
| 15 | ||
| 16 | PMU UNCORE (perf) driver: | |
| 17 | ||
| 18 | The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and | |
| 19 | L3C devices. Each PMU can be used to count up to 4 events | |
| 20 | simultaneously. The PMUs provide a description of their available events | |
| 21 | and configuration options under sysfs, see | |
| 22 | /sys/devices/uncore_<l3c_S/dmc_S/>; S is the socket id. | |
| 23 | ||
| 24 | The driver does not support sampling, therefore "perf record" will not | |
| 25 | work. Per-task perf sessions are also not supported. | |
| 26 | ||
| 27 | Examples: | |
| 28 | ||
| 29 | # perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1 | |
| 30 | ||
| 31 | # perf stat -a -e \ | |
| 32 | uncore_dmc_0/cnt_cycles/,\ | |
| 33 | uncore_dmc_0/data_transfers/,\ | |
| 34 | uncore_dmc_0/read_txns/,\ | |
| 35 | uncore_dmc_0/write_txns/ sleep 1 | |
| 36 | ||
| 37 | # perf stat -a -e \ | |
| 38 | uncore_l3c_0/read_request/,\ | |
| 39 | uncore_l3c_0/read_hit/,\ | |
| 40 | uncore_l3c_0/inv_request/,\ | |
| 41 | uncore_l3c_0/inv_hit/ sleep 1 |