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32fc3cd8 | 1 | ============== |
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2 | OpenRISC Linux |
3 | ============== | |
4 | ||
5 | This is a port of Linux to the OpenRISC class of microprocessors; the initial | |
6 | target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k). | |
7 | ||
8 | For information about OpenRISC processors and ongoing development: | |
9 | ||
32fc3cd8 | 10 | ======= ============================= |
d01e1f35 | 11 | website http://openrisc.io |
e4082de2 | 12 | email openrisc@lists.librecores.org |
32fc3cd8 | 13 | ======= ============================= |
61625766 JB |
14 | |
15 | --------------------------------------------------------------------- | |
16 | ||
17 | Build instructions for OpenRISC toolchain and Linux | |
18 | =================================================== | |
19 | ||
20 | In order to build and run Linux for OpenRISC, you'll need at least a basic | |
21 | toolchain and, perhaps, the architectural simulator. Steps to get these bits | |
22 | in place are outlined here. | |
23 | ||
e4082de2 SH |
24 | 1) Toolchain |
25 | ||
26 | Toolchain binaries can be obtained from openrisc.io or our github releases page. | |
27 | Instructions for building the different toolchains can be found on openrisc.io | |
28 | or Stafford's toolchain build and release scripts. | |
29 | ||
32fc3cd8 | 30 | ========== ================================================= |
e4082de2 SH |
31 | binaries https://github.com/openrisc/or1k-gcc/releases |
32 | toolchains https://openrisc.io/software | |
33 | building https://github.com/stffrdhrn/or1k-toolchain-build | |
32fc3cd8 | 34 | ========== ================================================= |
61625766 | 35 | |
e4082de2 | 36 | 2) Building |
61625766 | 37 | |
32fc3cd8 | 38 | Build the Linux kernel as usual:: |
61625766 | 39 | |
e4082de2 SH |
40 | make ARCH=openrisc defconfig |
41 | make ARCH=openrisc | |
61625766 | 42 | |
e4082de2 | 43 | 3) Running on FPGA (optional) |
61625766 | 44 | |
e4082de2 SH |
45 | The OpenRISC community typically uses FuseSoC to manage building and programming |
46 | an SoC into an FPGA. The below is an example of programming a De0 Nano | |
47 | development board with the OpenRISC SoC. During the build FPGA RTL is code | |
48 | downloaded from the FuseSoC IP cores repository and built using the FPGA vendor | |
49 | tools. Binaries are loaded onto the board with openocd. | |
61625766 | 50 | |
32fc3cd8 MCC |
51 | :: |
52 | ||
e4082de2 SH |
53 | git clone https://github.com/olofk/fusesoc |
54 | cd fusesoc | |
55 | sudo pip install -e . | |
61625766 | 56 | |
e4082de2 SH |
57 | fusesoc init |
58 | fusesoc build de0_nano | |
59 | fusesoc pgm de0_nano | |
61625766 | 60 | |
e4082de2 SH |
61 | openocd -f interface/altera-usb-blaster.cfg \ |
62 | -f board/or1k_generic.cfg | |
63 | ||
64 | telnet localhost 4444 | |
65 | > init | |
66 | > halt; load_image vmlinux ; reset | |
61625766 | 67 | |
e4082de2 | 68 | 4) Running on a Simulator (optional) |
61625766 | 69 | |
e4082de2 SH |
70 | QEMU is a processor emulator which we recommend for simulating the OpenRISC |
71 | platform. Please follow the OpenRISC instructions on the QEMU website to get | |
72 | Linux running on QEMU. You can build QEMU yourself, but your Linux distribution | |
73 | likely provides binary packages to support OpenRISC. | |
61625766 | 74 | |
32fc3cd8 | 75 | ============= ====================================================== |
e4082de2 | 76 | qemu openrisc https://wiki.qemu.org/Documentation/Platforms/OpenRISC |
32fc3cd8 | 77 | ============= ====================================================== |
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78 | |
79 | --------------------------------------------------------------------- | |
80 | ||
81 | Terminology | |
82 | =========== | |
83 | ||
84 | In the code, the following particles are used on symbols to limit the scope | |
85 | to more or less specific processor implementations: | |
86 | ||
32fc3cd8 | 87 | ========= ======================================= |
61625766 JB |
88 | openrisc: the OpenRISC class of processors |
89 | or1k: the OpenRISC 1000 family of processors | |
90 | or1200: the OpenRISC 1200 processor | |
32fc3cd8 | 91 | ========= ======================================= |
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92 | |
93 | --------------------------------------------------------------------- | |
94 | ||
95 | History | |
96 | ======== | |
97 | ||
32fc3cd8 | 98 | 18-11-2003 Matjaz Breskvar (phoenix@bsemi.com) |
61625766 JB |
99 | initial port of linux to OpenRISC/or32 architecture. |
100 | all the core stuff is implemented and seams usable. | |
101 | ||
32fc3cd8 | 102 | 08-12-2003 Matjaz Breskvar (phoenix@bsemi.com) |
61625766 JB |
103 | complete change of TLB miss handling. |
104 | rewrite of exceptions handling. | |
105 | fully functional sash-3.6 in default initrd. | |
106 | a much improved version with changes all around. | |
107 | ||
32fc3cd8 | 108 | 10-04-2004 Matjaz Breskvar (phoenix@bsemi.com) |
61625766 JB |
109 | alot of bugfixes all over. |
110 | ethernet support, functional http and telnet servers. | |
111 | running many standard linux apps. | |
112 | ||
32fc3cd8 | 113 | 26-06-2004 Matjaz Breskvar (phoenix@bsemi.com) |
61625766 JB |
114 | port to 2.6.x |
115 | ||
32fc3cd8 | 116 | 30-11-2004 Matjaz Breskvar (phoenix@bsemi.com) |
61625766 JB |
117 | lots of bugfixes and enhancments. |
118 | added opencores framebuffer driver. | |
119 | ||
32fc3cd8 | 120 | 09-10-2010 Jonas Bonn (jonas@southpole.se) |
61625766 | 121 | major rewrite to bring up to par with upstream Linux 2.6.36 |