Commit | Line | Data |
---|---|---|
db9a0975 | 1 | ============================== |
1da177e4 | 2 | IRQ affinity on IA64 platforms |
db9a0975 MCC |
3 | ============================== |
4 | ||
5 | 07.01.2002, Erich Focht <efocht@ess.nec.de> | |
1da177e4 LT |
6 | |
7 | ||
8 | By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be | |
9 | controlled. The behavior on IA64 platforms is slightly different from | |
e00b0ab8 | 10 | that described in Documentation/core-api/irq/irq-affinity.rst for i386 systems. |
1da177e4 LT |
11 | |
12 | Because of the usage of SAPIC mode and physical destination mode the | |
13 | IRQ target is one particular CPU and cannot be a mask of several | |
14 | CPUs. Only the first non-zero bit is taken into account. | |
15 | ||
16 | ||
db9a0975 MCC |
17 | Usage examples |
18 | ============== | |
1da177e4 LT |
19 | |
20 | The target CPU has to be specified as a hexadecimal CPU mask. The | |
21 | first non-zero bit is the selected CPU. This format has been kept for | |
22 | compatibility reasons with i386. | |
23 | ||
24 | Set the delivery mode of interrupt 41 to fixed and route the | |
db9a0975 MCC |
25 | interrupts to CPU #3 (logical CPU number) (2^3=0x08):: |
26 | ||
1da177e4 LT |
27 | echo "8" >/proc/irq/41/smp_affinity |
28 | ||
29 | Set the default route for IRQ number 41 to CPU 6 in lowest priority | |
db9a0975 MCC |
30 | delivery mode (redirectable):: |
31 | ||
1da177e4 LT |
32 | echo "r 40" >/proc/irq/41/smp_affinity |
33 | ||
db9a0975 MCC |
34 | The output of the command:: |
35 | ||
1da177e4 | 36 | cat /proc/irq/IRQ#/smp_affinity |
db9a0975 | 37 | |
1da177e4 LT |
38 | gives the target CPU mask for the specified interrupt vector. If the CPU |
39 | mask is preceded by the character "r", the interrupt is redirectable | |
40 | (i.e. lowest priority mode routing is used), otherwise its route is | |
41 | fixed. | |
42 | ||
43 | ||
44 | ||
db9a0975 MCC |
45 | Initialization and default behavior |
46 | =================================== | |
1da177e4 LT |
47 | |
48 | If the platform features IRQ redirection (info provided by SAL) all | |
49 | IO-SAPIC interrupts are initialized with CPU#0 as their default target | |
50 | and the routing is the so called "lowest priority mode" (actually | |
51 | fixed SAPIC mode with hint). The XTP chipset registers are used as hints | |
52 | for the IRQ routing. Currently in Linux XTP registers can have three | |
53 | values: | |
db9a0975 | 54 | |
1da177e4 LT |
55 | - minimal for an idle task, |
56 | - normal if any other task runs, | |
57 | - maximal if the CPU is going to be switched off. | |
db9a0975 | 58 | |
1da177e4 LT |
59 | The IRQ is routed to the CPU with lowest XTP register value, the |
60 | search begins at the default CPU. Therefore most of the interrupts | |
61 | will be handled by CPU #0. | |
62 | ||
63 | If the platform doesn't feature interrupt redirection IOSAPIC fixed | |
64 | routing is used. The target CPUs are distributed in a round robin | |
65 | manner. IRQs will be routed only to the selected target CPUs. Check | |
db9a0975 MCC |
66 | with:: |
67 | ||
1da177e4 LT |
68 | cat /proc/interrupts |
69 | ||
70 | ||
71 | ||
db9a0975 MCC |
72 | Comments |
73 | ======== | |
1da177e4 LT |
74 | |
75 | On large (multi-node) systems it is recommended to route the IRQs to | |
76 | the node to which the corresponding device is connected. | |
77 | For systems like the NEC AzusA we get IRQ node-affinity for free. This | |
78 | is because usually the chipsets on each node redirect the interrupts | |
79 | only to their own CPUs (as they cannot see the XTP registers on the | |
80 | other nodes). |