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2 | Linux I2C slave interface description |
3 | ===================================== | |
4 | ||
5 | by Wolfram Sang <wsa@sang-engineering.com> in 2014-15 | |
6 | ||
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7 | Linux can also be an I2C slave if the I2C controller in use has slave |
8 | functionality. For that to work, one needs slave support in the bus driver plus | |
9 | a hardware independent software backend providing the actual functionality. An | |
10 | example for the latter is the slave-eeprom driver, which acts as a dual memory | |
11 | driver. While another I2C master on the bus can access it like a regular | |
12 | EEPROM, the Linux I2C slave can access the content via sysfs and handle data as | |
13 | needed. The backend driver and the I2C bus driver communicate via events. Here | |
14 | is a small graph visualizing the data flow and the means by which data is | |
15 | transported. The dotted line marks only one example. The backend could also | |
ccf988b6 | 16 | use a character device, be in-kernel only, or something completely different:: |
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17 | |
18 | ||
19 | e.g. sysfs I2C slave events I/O registers | |
20 | +-----------+ v +---------+ v +--------+ v +------------+ | |
21 | | Userspace +........+ Backend +-----------+ Driver +-----+ Controller | | |
22 | +-----------+ +---------+ +--------+ +------------+ | |
23 | | | | |
24 | ----------------------------------------------------------------+-- I2C | |
25 | --------------------------------------------------------------+---- Bus | |
26 | ||
27 | Note: Technically, there is also the I2C core between the backend and the | |
28 | driver. However, at this time of writing, the layer is transparent. | |
29 | ||
30 | ||
31 | User manual | |
32 | =========== | |
33 | ||
34 | I2C slave backends behave like standard I2C clients. So, you can instantiate | |
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35 | them as described in the document instantiating-devices.rst. The only |
36 | difference is that i2c slave backends have their own address space. So, you | |
37 | have to add 0x1000 to the address you would originally request. An example for | |
cfa0327b | 38 | instantiating the slave-eeprom driver from userspace at the 7 bit address 0x64 |
ccf988b6 | 39 | on bus 1:: |
7c603750 | 40 | |
cfa0327b | 41 | # echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-1/new_device |
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42 | |
43 | Each backend should come with separate documentation to describe its specific | |
44 | behaviour and setup. | |
45 | ||
46 | ||
47 | Developer manual | |
48 | ================ | |
49 | ||
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50 | First, the events which are used by the bus driver and the backend will be |
51 | described in detail. After that, some implementation hints for extending bus | |
52 | drivers and writing backends will be given. | |
53 | ||
54 | ||
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55 | I2C slave events |
56 | ---------------- | |
57 | ||
ccf988b6 | 58 | The bus driver sends an event to the backend using the following function:: |
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59 | |
60 | ret = i2c_slave_event(client, event, &val) | |
61 | ||
2f07c05f | 62 | 'client' describes the I2C slave device. 'event' is one of the special event |
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63 | types described hereafter. 'val' holds an u8 value for the data byte to be |
64 | read/written and is thus bidirectional. The pointer to val must always be | |
65 | provided even if val is not used for an event, i.e. don't use NULL here. 'ret' | |
66 | is the return value from the backend. Mandatory events must be provided by the | |
67 | bus drivers and must be checked for by backend drivers. | |
68 | ||
69 | Event types: | |
70 | ||
71 | * I2C_SLAVE_WRITE_REQUESTED (mandatory) | |
72 | ||
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73 | 'val': unused |
74 | ||
09a7bab6 | 75 | 'ret': 0 if the backend is ready, otherwise some errno |
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76 | |
77 | Another I2C master wants to write data to us. This event should be sent once | |
78 | our own address and the write bit was detected. The data did not arrive yet, so | |
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79 | there is nothing to process or return. After returning, the bus driver must |
80 | always ack the address phase. If 'ret' is zero, backend initialization or | |
81 | wakeup is done and further data may be received. If 'ret' is an errno, the bus | |
82 | driver should nack all incoming bytes until the next stop condition to enforce | |
83 | a retry of the transmission. | |
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84 | |
85 | * I2C_SLAVE_READ_REQUESTED (mandatory) | |
86 | ||
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87 | 'val': backend returns first byte to be sent |
88 | ||
89 | 'ret': always 0 | |
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90 | |
91 | Another I2C master wants to read data from us. This event should be sent once | |
92 | our own address and the read bit was detected. After returning, the bus driver | |
93 | should transmit the first byte. | |
94 | ||
95 | * I2C_SLAVE_WRITE_RECEIVED (mandatory) | |
96 | ||
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97 | 'val': bus driver delivers received byte |
98 | ||
99 | 'ret': 0 if the byte should be acked, some errno if the byte should be nacked | |
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100 | |
101 | Another I2C master has sent a byte to us which needs to be set in 'val'. If 'ret' | |
102 | is zero, the bus driver should ack this byte. If 'ret' is an errno, then the byte | |
103 | should be nacked. | |
104 | ||
105 | * I2C_SLAVE_READ_PROCESSED (mandatory) | |
106 | ||
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107 | 'val': backend returns next byte to be sent |
108 | ||
109 | 'ret': always 0 | |
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110 | |
111 | The bus driver requests the next byte to be sent to another I2C master in | |
112 | 'val'. Important: This does not mean that the previous byte has been acked, it | |
113 | only means that the previous byte is shifted out to the bus! To ensure seamless | |
114 | transmission, most hardware requests the next byte when the previous one is | |
115 | still shifted out. If the master sends NACK and stops reading after the byte | |
116 | currently shifted out, this byte requested here is never used. It very likely | |
117 | needs to be sent again on the next I2C_SLAVE_READ_REQUEST, depending a bit on | |
118 | your backend, though. | |
119 | ||
120 | * I2C_SLAVE_STOP (mandatory) | |
121 | ||
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122 | 'val': unused |
123 | ||
124 | 'ret': always 0 | |
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125 | |
126 | A stop condition was received. This can happen anytime and the backend should | |
127 | reset its state machine for I2C transfers to be able to receive new requests. | |
128 | ||
129 | ||
130 | Software backends | |
131 | ----------------- | |
132 | ||
133 | If you want to write a software backend: | |
134 | ||
135 | * use a standard i2c_driver and its matching mechanisms | |
136 | * write the slave_callback which handles the above slave events | |
137 | (best using a state machine) | |
138 | * register this callback via i2c_slave_register() | |
139 | ||
140 | Check the i2c-slave-eeprom driver as an example. | |
141 | ||
142 | ||
143 | Bus driver support | |
144 | ------------------ | |
145 | ||
146 | If you want to add slave support to the bus driver: | |
147 | ||
148 | * implement calls to register/unregister the slave and add those to the | |
2f07c05f | 149 | struct i2c_algorithm. When registering, you probably need to set the I2C |
7c603750 | 150 | slave address and enable slave specific interrupts. If you use runtime pm, you |
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151 | should use pm_runtime_get_sync() because your device usually needs to be |
152 | powered on always to be able to detect its slave address. When unregistering, | |
153 | do the inverse of the above. | |
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154 | |
155 | * Catch the slave interrupts and send appropriate i2c_slave_events to the backend. | |
156 | ||
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157 | Note that most hardware supports being master _and_ slave on the same bus. So, |
158 | if you extend a bus driver, please make sure that the driver supports that as | |
159 | well. In almost all cases, slave support does not need to disable the master | |
160 | functionality. | |
161 | ||
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162 | Check the i2c-rcar driver as an example. |
163 | ||
164 | ||
165 | About ACK/NACK | |
166 | -------------- | |
167 | ||
168 | It is good behaviour to always ACK the address phase, so the master knows if a | |
169 | device is basically present or if it mysteriously disappeared. Using NACK to | |
170 | state being busy is troublesome. SMBus demands to always ACK the address phase, | |
171 | while the I2C specification is more loose on that. Most I2C controllers also | |
172 | automatically ACK when detecting their slave addresses, so there is no option | |
173 | to NACK them. For those reasons, this API does not support NACK in the address | |
174 | phase. | |
175 | ||
176 | Currently, there is no slave event to report if the master did ACK or NACK a | |
177 | byte when it reads from us. We could make this an optional event if the need | |
178 | arises. However, cases should be extremely rare because the master is expected | |
179 | to send STOP after that and we have an event for that. Also, keep in mind not | |
180 | all I2C controllers have the possibility to report that event. | |
181 | ||
182 | ||
183 | About buffers | |
184 | ------------- | |
185 | ||
186 | During development of this API, the question of using buffers instead of just | |
187 | bytes came up. Such an extension might be possible, usefulness is unclear at | |
188 | this time of writing. Some points to keep in mind when using buffers: | |
189 | ||
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190 | * Buffers should be opt-in and backend drivers will always have to support |
191 | byte-based transactions as the ultimate fallback anyhow because this is how | |
192 | the majority of HW works. | |
193 | ||
194 | * For backends simulating hardware registers, buffers are largely not helpful | |
195 | because after each byte written an action should be immediately triggered. | |
196 | For reads, the data kept in the buffer might get stale if the backend just | |
197 | updated a register because of internal processing. | |
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198 | |
199 | * A master can send STOP at any time. For partially transferred buffers, this | |
200 | means additional code to handle this exception. Such code tends to be | |
201 | error-prone. |