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2138f885 GR |
1 | .. SPDX-License-Identifier: GPL-2.0 |
2 | ||
3 | Kernel driver max16601 | |
4 | ====================== | |
5 | ||
6 | Supported chips: | |
7 | ||
66102281 GR |
8 | * Maxim MAX16508 |
9 | ||
10 | Prefix: 'max16508' | |
11 | ||
12 | Addresses scanned: - | |
13 | ||
14 | Datasheet: Not published | |
15 | ||
a6f7c5d0 GR |
16 | * Maxim MAX16600 |
17 | ||
18 | Prefix: 'max16600' | |
19 | ||
20 | Addresses scanned: - | |
21 | ||
22 | Datasheet: Not published | |
23 | ||
2138f885 GR |
24 | * Maxim MAX16601 |
25 | ||
26 | Prefix: 'max16601' | |
27 | ||
28 | Addresses scanned: - | |
29 | ||
30 | Datasheet: Not published | |
31 | ||
e5c498cc AO |
32 | * Maxim MAX16602 |
33 | ||
34 | Prefix: 'max16602' | |
35 | ||
36 | Addresses scanned: - | |
37 | ||
38 | Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX16602.pdf | |
39 | ||
2138f885 GR |
40 | Author: Guenter Roeck <linux@roeck-us.net> |
41 | ||
42 | ||
43 | Description | |
44 | ----------- | |
45 | ||
66102281 | 46 | This driver supports the MAX16508 VR13 Dual-Output Voltage Regulator |
a6f7c5d0 GR |
47 | as well as the MAX16600, MAX16601, and MAX16602 VR13.HC Dual-Output |
48 | Voltage Regulator chipsets. | |
2138f885 GR |
49 | |
50 | The driver is a client driver to the core PMBus driver. | |
51 | Please see Documentation/hwmon/pmbus.rst for details on PMBus client drivers. | |
52 | ||
53 | ||
54 | Usage Notes | |
55 | ----------- | |
56 | ||
57 | This driver does not auto-detect devices. You will have to instantiate the | |
58 | devices explicitly. Please see Documentation/i2c/instantiating-devices.rst for | |
59 | details. | |
60 | ||
61 | ||
62 | Platform data support | |
63 | --------------------- | |
64 | ||
65 | The driver supports standard PMBus driver platform data. | |
66 | ||
67 | ||
68 | Sysfs entries | |
69 | ------------- | |
70 | ||
71 | The following attributes are supported. | |
72 | ||
220c404d GR |
73 | =============================== =============================================== |
74 | in1_label "vin1" | |
75 | in1_input VCORE input voltage. | |
76 | in1_alarm Input voltage alarm. | |
77 | ||
78 | in2_label "vout1" | |
79 | in2_input VCORE output voltage. | |
80 | in2_alarm Output voltage alarm. | |
81 | ||
82 | curr1_label "iin1" | |
83 | curr1_input VCORE input current, derived from duty cycle | |
84 | and output current. | |
85 | curr1_max Maximum input current. | |
86 | curr1_max_alarm Current high alarm. | |
87 | ||
88 | curr[P+2]_label "iin1.P" | |
89 | curr[P+2]_input VCORE phase P input current. | |
90 | ||
91 | curr[N+2]_label "iin2" | |
92 | curr[N+2]_input VCORE input current, derived from sensor | |
93 | element. | |
94 | 'N' is the number of enabled/populated phases. | |
95 | ||
96 | curr[N+3]_label "iin3" | |
97 | curr[N+3]_input VSA input current. | |
98 | ||
99 | curr[N+4]_label "iout1" | |
100 | curr[N+4]_input VCORE output current. | |
101 | curr[N+4]_crit Critical output current. | |
102 | curr[N+4]_crit_alarm Output current critical alarm. | |
103 | curr[N+4]_max Maximum output current. | |
104 | curr[N+4]_max_alarm Output current high alarm. | |
105 | ||
106 | curr[N+P+5]_label "iout1.P" | |
107 | curr[N+P+5]_input VCORE phase P output current. | |
108 | ||
109 | curr[2*N+5]_label "iout3" | |
110 | curr[2*N+5]_input VSA output current. | |
111 | curr[2*N+5]_highest Historical maximum VSA output current. | |
112 | curr[2*N+5]_reset_history Write any value to reset curr21_highest. | |
113 | curr[2*N+5]_crit Critical output current. | |
114 | curr[2*N+5]_crit_alarm Output current critical alarm. | |
115 | curr[2*N+5]_max Maximum output current. | |
116 | curr[2*N+5]_max_alarm Output current high alarm. | |
117 | ||
118 | power1_label "pin1" | |
119 | power1_input Input power, derived from duty cycle and output | |
120 | current. | |
121 | power1_alarm Input power alarm. | |
122 | ||
123 | power2_label "pin2" | |
124 | power2_input Input power, derived from input current sensor. | |
125 | ||
126 | power3_label "pout" | |
127 | power3_input Output power. | |
128 | ||
129 | temp1_input VCORE temperature. | |
130 | temp1_crit Critical high temperature. | |
131 | temp1_crit_alarm Chip temperature critical high alarm. | |
132 | temp1_max Maximum temperature. | |
133 | temp1_max_alarm Chip temperature high alarm. | |
134 | ||
135 | temp2_input TSENSE_0 temperature | |
136 | temp3_input TSENSE_1 temperature | |
137 | temp4_input TSENSE_2 temperature | |
138 | temp5_input TSENSE_3 temperature | |
139 | ||
140 | temp6_input VSA temperature. | |
141 | temp6_crit Critical high temperature. | |
142 | temp6_crit_alarm Chip temperature critical high alarm. | |
143 | temp6_max Maximum temperature. | |
144 | temp6_max_alarm Chip temperature high alarm. | |
145 | =============================== =============================================== |