drm/i915/uc: Move uc firmware layout definitions to dedicated file
[linux-2.6-block.git] / Documentation / gpu / i915.rst
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1===========================
2 drm/i915 Intel GFX Driver
3===========================
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4
5The drm/i915 driver supports all (with the exception of some very early
6models) integrated GFX chipsets with both Intel display and rendering
7blocks. This excludes a set of SoC platforms with an SGX rendering unit,
8those have basic support through the gma500 drm driver.
9
10Core Driver Infrastructure
22554020 11==========================
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12
13This section covers core driver infrastructure used by both the display
14and the GEM parts of the driver.
15
16Runtime Power Management
22554020 17------------------------
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18
19.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
20 :doc: runtime pm
21
22.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
23 :internal:
24
25.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
26 :internal:
27
28Interrupt Handling
22554020 29------------------
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30
31.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
32 :doc: interrupt handling
33
34.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init
36
37.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
38 :functions: intel_runtime_pm_disable_interrupts
39
40.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
41 :functions: intel_runtime_pm_enable_interrupts
42
43Intel GVT-g Guest Support(vGPU)
22554020 44-------------------------------
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45
46.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
47 :doc: Intel GVT-g guest support
48
49.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
50 :internal:
51
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52Intel GVT-g Host Support(vGPU device model)
53-------------------------------------------
54
55.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
56 :doc: Intel GVT-g host support
57
58.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
59 :internal:
60
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61Workarounds
62-----------
63
bcc8737d 64.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c
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65 :doc: Hardware workarounds
66
ca00c2b9 67Display Hardware Handling
22554020 68=========================
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69
70This section covers everything related to the display hardware including
71the mode setting infrastructure, plane, sprite and cursor handling and
72display, output probing and related topics.
73
74Mode Setting Infrastructure
22554020 75---------------------------
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76
77The i915 driver is thus far the only DRM driver which doesn't use the
78common DRM helper code to implement mode setting sequences. Thus it has
79its own tailor-made infrastructure for executing a display configuration
80change.
81
82Frontbuffer Tracking
22554020 83--------------------
ca00c2b9 84
6800d9a5 85.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
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86 :doc: frontbuffer tracking
87
6800d9a5 88.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h
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89 :internal:
90
6800d9a5 91.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
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92 :internal:
93
94.. kernel-doc:: drivers/gpu/drm/i915/i915_gem.c
95 :functions: i915_gem_track_fb
96
97Display FIFO Underrun Reporting
22554020 98-------------------------------
ca00c2b9 99
6800d9a5 100.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
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101 :doc: fifo underrun handling
102
6800d9a5 103.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
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104 :internal:
105
106Plane Configuration
22554020 107-------------------
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108
109This section covers plane configuration and composition with the primary
110plane, sprites, cursors and overlays. This includes the infrastructure
111to do atomic vsync'ed updates of all this state and also tightly coupled
112topics like watermark setup and computation, framebuffer compression and
113panel self refresh.
114
115Atomic Plane Helpers
22554020 116--------------------
ca00c2b9 117
6800d9a5 118.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
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119 :doc: atomic plane helpers
120
6800d9a5 121.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
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122 :internal:
123
124Output Probing
22554020 125--------------
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126
127This section covers output probing and related infrastructure like the
128hotplug interrupt storm detection and mitigation code. Note that the
129i915 driver still uses most of the common DRM helper code for output
130probing, so those sections fully apply.
131
132Hotplug
22554020 133-------
ca00c2b9 134
6800d9a5 135.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
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136 :doc: Hotplug
137
6800d9a5 138.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
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139 :internal:
140
141High Definition Audio
22554020 142---------------------
ca00c2b9 143
6800d9a5 144.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
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145 :doc: High Definition Audio over HDMI and Display Port
146
6800d9a5 147.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
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148 :internal:
149
150.. kernel-doc:: include/drm/i915_component.h
151 :internal:
152
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153Intel HDMI LPE Audio Support
154----------------------------
155
6800d9a5 156.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
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157 :doc: LPE Audio integration for HDMI or DP playback
158
6800d9a5 159.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
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160 :internal:
161
ca00c2b9 162Panel Self Refresh PSR (PSR/SRD)
22554020 163--------------------------------
ca00c2b9 164
6800d9a5 165.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
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166 :doc: Panel Self Refresh (PSR/SRD)
167
6800d9a5 168.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
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169 :internal:
170
171Frame Buffer Compression (FBC)
22554020 172------------------------------
ca00c2b9 173
6800d9a5 174.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
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175 :doc: Frame Buffer Compression (FBC)
176
6800d9a5 177.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
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178 :internal:
179
180Display Refresh Rate Switching (DRRS)
22554020 181-------------------------------------
ca00c2b9 182
6800d9a5 183.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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184 :doc: Display Refresh Rate Switching (DRRS)
185
6800d9a5 186.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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187 :functions: intel_dp_set_drrs_state
188
6800d9a5 189.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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190 :functions: intel_edp_drrs_enable
191
6800d9a5 192.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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193 :functions: intel_edp_drrs_disable
194
6800d9a5 195.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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196 :functions: intel_edp_drrs_invalidate
197
6800d9a5 198.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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199 :functions: intel_edp_drrs_flush
200
6800d9a5 201.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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202 :functions: intel_dp_drrs_init
203
204DPIO
22554020 205----
ca00c2b9 206
6800d9a5 207.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c
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208 :doc: DPIO
209
210CSR firmware support for DMC
22554020 211----------------------------
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212
213.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
214 :doc: csr support for dmc
215
216.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
217 :internal:
218
219Video BIOS Table (VBT)
22554020 220----------------------
ca00c2b9 221
6800d9a5 222.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
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223 :doc: Video BIOS Table (VBT)
224
6800d9a5 225.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
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226 :internal:
227
6800d9a5 228.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h
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229 :internal:
230
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231Display clocks
232--------------
233
6800d9a5 234.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
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235 :doc: CDCLK / RAWCLK
236
6800d9a5 237.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
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238 :internal:
239
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240Display PLLs
241------------
242
6800d9a5 243.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
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244 :doc: Display PLLs
245
6800d9a5 246.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
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247 :internal:
248
6800d9a5 249.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
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250 :internal:
251
ca00c2b9 252Memory Management and Command Submission
22554020 253========================================
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254
255This sections covers all things related to the GEM implementation in the
256i915 driver.
257
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258Intel GPU Basics
259----------------
260
261An Intel GPU has multiple engines. There are several engine types.
262
263- RCS engine is for rendering 3D and performing compute, this is named
264 `I915_EXEC_RENDER` in user space.
265- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user
266 space.
267- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD`
268 in user space
269- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user
270 space.
271- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine;
272 instead it is to be used by user space to specify a default rendering
273 engine (for 3D) that may or may not be the same as RCS.
274
275The Intel GPU family is a family of integrated GPU's using Unified
276Memory Access. For having the GPU "do work", user space will feed the
277GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
278or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
279instruct the GPU to perform work (for example rendering) and that work
280needs memory from which to read and memory to which to write. All memory
281is encapsulated within GEM buffer objects (usually created with the ioctl
282`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
283to create will also list all GEM buffer objects that the batchbuffer reads
284and/or writes. For implementation details of memory management see
285`GEM BO Management Implementation Details`_.
286
287The i915 driver allows user space to create a context via the ioctl
288`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
289integer. Such a context should be viewed by user-space as -loosely-
290analogous to the idea of a CPU process of an operating system. The i915
291driver guarantees that commands issued to a fixed context are to be
292executed so that writes of a previously issued command are seen by
293reads of following commands. Actions issued between different contexts
294(even if from the same file descriptor) are NOT given that guarantee
295and the only way to synchronize across contexts (even from the same
296file descriptor) is through the use of fences. At least as far back as
297Gen4, also have that a context carries with it a GPU HW context;
298the HW context is essentially (most of atleast) the state of a GPU.
299In addition to the ordering guarantees, the kernel will restore GPU
300state via HW context when commands are issued to a context, this saves
301user space the need to restore (most of atleast) the GPU state at the
302start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
303work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
304to identify what context to use with the command.
305
306The GPU has its own memory management and address space. The kernel
307driver maintains the memory translation table for the GPU. For older
308GPUs (i.e. those before Gen8), there is a single global such translation
309table, a global Graphics Translation Table (GTT). For newer generation
310GPUs each context has its own translation table, called Per-Process
311Graphics Translation Table (PPGTT). Of important note, is that although
312PPGTT is named per-process it is actually per context. When user space
313submits a batchbuffer, the kernel walks the list of GEM buffer objects
314used by the batchbuffer and guarantees that not only is the memory of
315each such GEM buffer object resident but it is also present in the
316(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
317then it is given an address. Two consequences of this are: the kernel
318needs to edit the batchbuffer submitted to write the correct value of
319the GPU address when a GEM BO is assigned a GPU address and the kernel
320might evict a different GEM BO from the (PP)GTT to make address room
321for another GEM BO. Consequently, the ioctls submitting a batchbuffer
322for execution also include a list of all locations within buffers that
323refer to GPU-addresses so that the kernel can edit the buffer correctly.
324This process is dubbed relocation.
325
326GEM BO Management Implementation Details
327----------------------------------------
328
329.. kernel-doc:: drivers/gpu/drm/i915/i915_vma.h
330 :doc: Virtual Memory Address
331
332Buffer Object Eviction
333----------------------
334
335This section documents the interface functions for evicting buffer
336objects to make space available in the virtual gpu address spaces. Note
337that this is mostly orthogonal to shrinking buffer objects caches, which
338has the goal to make main memory (shared with the gpu through the
339unified memory architecture) available.
340
341.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
342 :internal:
343
344Buffer Object Memory Shrinking
345------------------------------
346
347This section documents the interface function for shrinking memory usage
348of buffer object caches. Shrinking is used to make main memory
349available. Note that this is mostly orthogonal to evicting buffer
350objects, which has the goal to make space in gpu virtual address spaces.
351
8a6f43d4 352.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
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353 :internal:
354
ca00c2b9 355Batchbuffer Parsing
22554020 356-------------------
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357
358.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
359 :doc: batch buffer command parser
360
361.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
362 :internal:
363
364Batchbuffer Pools
22554020 365-----------------
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366
367.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c
368 :doc: batch pool
369
370.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c
371 :internal:
372
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373User Batchbuffer Execution
374--------------------------
375
8a6f43d4 376.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
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377 :doc: User command execution
378
ca00c2b9 379Logical Rings, Logical Ring Contexts and Execlists
22554020 380--------------------------------------------------
ca00c2b9 381
bcc8737d 382.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c
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383 :doc: Logical Rings, Logical Ring Contexts and Execlists
384
ca00c2b9 385Global GTT views
22554020 386----------------
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387
388.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
389 :doc: Global GTT views
390
391.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
392 :internal:
393
394GTT Fences and Swizzling
22554020 395------------------------
ca00c2b9 396
ebc896db 397.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
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398 :internal:
399
400Global GTT Fence Handling
22554020 401~~~~~~~~~~~~~~~~~~~~~~~~~
ca00c2b9 402
ebc896db 403.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
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404 :doc: fence register handling
405
406Hardware Tiling and Swizzling Details
22554020 407~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ca00c2b9 408
ebc896db 409.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
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410 :doc: tiling swizzling details
411
412Object Tiling IOCTLs
22554020 413--------------------
ca00c2b9 414
8a6f43d4 415.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
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416 :internal:
417
8a6f43d4 418.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
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419 :doc: buffer object tiling
420
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421WOPCM
422=====
423
424WOPCM Layout
425------------
426
427.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c
428 :doc: WOPCM Layout
429
ca00c2b9 430GuC
22554020 431===
ca00c2b9 432
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433Firmware Layout
434-------------------
435
abf30f23 436.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
199ddded
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437 :doc: Firmware Layout
438
ca00c2b9 439GuC-specific firmware loader
22554020 440----------------------------
ca00c2b9 441
dbbff8c3 442.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
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443 :internal:
444
445GuC-based command submission
22554020 446----------------------------
ca00c2b9 447
dbbff8c3 448.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
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449 :doc: GuC-based command submission
450
dbbff8c3 451.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
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452 :internal:
453
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454GuC Address Space
455-----------------
456
dbbff8c3 457.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
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458 :doc: GuC Address Space
459
ca00c2b9 460Tracing
22554020 461=======
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462
463This sections covers all things related to the tracepoints implemented
464in the i915 driver.
465
466i915_ppgtt_create and i915_ppgtt_release
22554020 467----------------------------------------
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468
469.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
470 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints
471
472i915_context_create and i915_context_free
22554020 473-----------------------------------------
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474
475.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
476 :doc: i915_context_create and i915_context_free tracepoints
477
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478Perf
479====
480
481Overview
482--------
483.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
484 :doc: i915 Perf Overview
485
486Comparison with Core Perf
487-------------------------
488.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
489 :doc: i915 Perf History and Comparison with Core Perf
490
491i915 Driver Entry Points
492------------------------
493
494This section covers the entrypoints exported outside of i915_perf.c to
495integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl.
496
497.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
498 :functions: i915_perf_init
499.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
500 :functions: i915_perf_fini
501.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
502 :functions: i915_perf_register
503.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
504 :functions: i915_perf_unregister
505.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
506 :functions: i915_perf_open_ioctl
507.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
508 :functions: i915_perf_release
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509.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
510 :functions: i915_perf_add_config_ioctl
511.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
512 :functions: i915_perf_remove_config_ioctl
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513
514i915 Perf Stream
515----------------
516
517This section covers the stream-semantics-agnostic structures and functions
518for representing an i915 perf stream FD and associated file operations.
519
520.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
521 :functions: i915_perf_stream
522.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
523 :functions: i915_perf_stream_ops
524
525.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
526 :functions: read_properties_unlocked
527.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
528 :functions: i915_perf_open_ioctl_locked
529.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
530 :functions: i915_perf_destroy_locked
531.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
532 :functions: i915_perf_read
533.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
534 :functions: i915_perf_ioctl
535.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
536 :functions: i915_perf_enable_locked
537.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
538 :functions: i915_perf_disable_locked
539.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
540 :functions: i915_perf_poll
541.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
542 :functions: i915_perf_poll_locked
543
544i915 Perf Observation Architecture Stream
545-----------------------------------------
546
547.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
548 :functions: i915_oa_ops
549
550.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
551 :functions: i915_oa_stream_init
552.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
553 :functions: i915_oa_read
554.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
555 :functions: i915_oa_stream_enable
556.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
557 :functions: i915_oa_stream_disable
558.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
559 :functions: i915_oa_wait_unlocked
560.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
561 :functions: i915_oa_poll_wait
562
563All i915 Perf Internals
564-----------------------
565
566This section simply includes all currently documented i915 perf internals, in
567no particular order, but may include some more minor utilities or platform
568specific details than found in the more high-level sections.
569
570.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
571 :internal:
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572
573Style
574=====
575
576The drm/i915 driver codebase has some style rules in addition to (and, in some
577cases, deviating from) the kernel coding style.
578
579Register macro definition style
580-------------------------------
581
582The style guide for ``i915_reg.h``.
583
584.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
585 :doc: The i915 register macro definition style guide