Merge tag 'drm-intel-next-2019-10-07' of git://anongit.freedesktop.org/drm/drm-intel...
[linux-2.6-block.git] / Documentation / gpu / i915.rst
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1===========================
2 drm/i915 Intel GFX Driver
3===========================
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4
5The drm/i915 driver supports all (with the exception of some very early
6models) integrated GFX chipsets with both Intel display and rendering
7blocks. This excludes a set of SoC platforms with an SGX rendering unit,
8those have basic support through the gma500 drm driver.
9
10Core Driver Infrastructure
22554020 11==========================
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12
13This section covers core driver infrastructure used by both the display
14and the GEM parts of the driver.
15
16Runtime Power Management
22554020 17------------------------
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18
19.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
20 :doc: runtime pm
21
22.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
23 :internal:
24
25.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
26 :internal:
27
28Interrupt Handling
22554020 29------------------
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30
31.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
32 :doc: interrupt handling
33
34.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init
36
37.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
38 :functions: intel_runtime_pm_disable_interrupts
39
40.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
41 :functions: intel_runtime_pm_enable_interrupts
42
43Intel GVT-g Guest Support(vGPU)
22554020 44-------------------------------
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45
46.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
47 :doc: Intel GVT-g guest support
48
49.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
50 :internal:
51
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52Intel GVT-g Host Support(vGPU device model)
53-------------------------------------------
54
55.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
56 :doc: Intel GVT-g host support
57
58.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
59 :internal:
60
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61Workarounds
62-----------
63
bcc8737d 64.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c
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65 :doc: Hardware workarounds
66
ca00c2b9 67Display Hardware Handling
22554020 68=========================
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69
70This section covers everything related to the display hardware including
71the mode setting infrastructure, plane, sprite and cursor handling and
72display, output probing and related topics.
73
74Mode Setting Infrastructure
22554020 75---------------------------
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76
77The i915 driver is thus far the only DRM driver which doesn't use the
78common DRM helper code to implement mode setting sequences. Thus it has
79its own tailor-made infrastructure for executing a display configuration
80change.
81
82Frontbuffer Tracking
22554020 83--------------------
ca00c2b9 84
6800d9a5 85.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
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86 :doc: frontbuffer tracking
87
6800d9a5 88.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h
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89 :internal:
90
6800d9a5 91.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
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92 :internal:
93
ca00c2b9 94Display FIFO Underrun Reporting
22554020 95-------------------------------
ca00c2b9 96
6800d9a5 97.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
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98 :doc: fifo underrun handling
99
6800d9a5 100.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
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101 :internal:
102
103Plane Configuration
22554020 104-------------------
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105
106This section covers plane configuration and composition with the primary
107plane, sprites, cursors and overlays. This includes the infrastructure
108to do atomic vsync'ed updates of all this state and also tightly coupled
109topics like watermark setup and computation, framebuffer compression and
110panel self refresh.
111
112Atomic Plane Helpers
22554020 113--------------------
ca00c2b9 114
6800d9a5 115.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
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116 :doc: atomic plane helpers
117
6800d9a5 118.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
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119 :internal:
120
121Output Probing
22554020 122--------------
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123
124This section covers output probing and related infrastructure like the
125hotplug interrupt storm detection and mitigation code. Note that the
126i915 driver still uses most of the common DRM helper code for output
127probing, so those sections fully apply.
128
129Hotplug
22554020 130-------
ca00c2b9 131
6800d9a5 132.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
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133 :doc: Hotplug
134
6800d9a5 135.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
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136 :internal:
137
138High Definition Audio
22554020 139---------------------
ca00c2b9 140
6800d9a5 141.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
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142 :doc: High Definition Audio over HDMI and Display Port
143
6800d9a5 144.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
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145 :internal:
146
147.. kernel-doc:: include/drm/i915_component.h
148 :internal:
149
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150Intel HDMI LPE Audio Support
151----------------------------
152
6800d9a5 153.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
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154 :doc: LPE Audio integration for HDMI or DP playback
155
6800d9a5 156.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
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157 :internal:
158
ca00c2b9 159Panel Self Refresh PSR (PSR/SRD)
22554020 160--------------------------------
ca00c2b9 161
6800d9a5 162.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
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163 :doc: Panel Self Refresh (PSR/SRD)
164
6800d9a5 165.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
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166 :internal:
167
168Frame Buffer Compression (FBC)
22554020 169------------------------------
ca00c2b9 170
6800d9a5 171.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
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172 :doc: Frame Buffer Compression (FBC)
173
6800d9a5 174.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
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175 :internal:
176
177Display Refresh Rate Switching (DRRS)
22554020 178-------------------------------------
ca00c2b9 179
6800d9a5 180.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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181 :doc: Display Refresh Rate Switching (DRRS)
182
6800d9a5 183.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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184 :functions: intel_dp_set_drrs_state
185
6800d9a5 186.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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187 :functions: intel_edp_drrs_enable
188
6800d9a5 189.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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190 :functions: intel_edp_drrs_disable
191
6800d9a5 192.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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193 :functions: intel_edp_drrs_invalidate
194
6800d9a5 195.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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196 :functions: intel_edp_drrs_flush
197
6800d9a5 198.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
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199 :functions: intel_dp_drrs_init
200
201DPIO
22554020 202----
ca00c2b9 203
6800d9a5 204.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c
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205 :doc: DPIO
206
207CSR firmware support for DMC
22554020 208----------------------------
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209
210.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
211 :doc: csr support for dmc
212
213.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
214 :internal:
215
216Video BIOS Table (VBT)
22554020 217----------------------
ca00c2b9 218
6800d9a5 219.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
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220 :doc: Video BIOS Table (VBT)
221
6800d9a5 222.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
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223 :internal:
224
6800d9a5 225.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h
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226 :internal:
227
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228Display clocks
229--------------
230
6800d9a5 231.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
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232 :doc: CDCLK / RAWCLK
233
6800d9a5 234.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
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235 :internal:
236
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237Display PLLs
238------------
239
6800d9a5 240.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
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241 :doc: Display PLLs
242
6800d9a5 243.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
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244 :internal:
245
6800d9a5 246.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
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247 :internal:
248
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249Display State Buffer
250--------------------
251
252.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
253 :doc: DSB
254
255.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
256 :internal:
257
ca00c2b9 258Memory Management and Command Submission
22554020 259========================================
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260
261This sections covers all things related to the GEM implementation in the
262i915 driver.
263
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264Intel GPU Basics
265----------------
266
267An Intel GPU has multiple engines. There are several engine types.
268
269- RCS engine is for rendering 3D and performing compute, this is named
270 `I915_EXEC_RENDER` in user space.
271- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user
272 space.
273- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD`
274 in user space
275- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user
276 space.
277- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine;
278 instead it is to be used by user space to specify a default rendering
279 engine (for 3D) that may or may not be the same as RCS.
280
281The Intel GPU family is a family of integrated GPU's using Unified
282Memory Access. For having the GPU "do work", user space will feed the
283GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
284or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
285instruct the GPU to perform work (for example rendering) and that work
286needs memory from which to read and memory to which to write. All memory
287is encapsulated within GEM buffer objects (usually created with the ioctl
288`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
289to create will also list all GEM buffer objects that the batchbuffer reads
290and/or writes. For implementation details of memory management see
291`GEM BO Management Implementation Details`_.
292
293The i915 driver allows user space to create a context via the ioctl
294`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
295integer. Such a context should be viewed by user-space as -loosely-
296analogous to the idea of a CPU process of an operating system. The i915
297driver guarantees that commands issued to a fixed context are to be
298executed so that writes of a previously issued command are seen by
299reads of following commands. Actions issued between different contexts
300(even if from the same file descriptor) are NOT given that guarantee
301and the only way to synchronize across contexts (even from the same
302file descriptor) is through the use of fences. At least as far back as
303Gen4, also have that a context carries with it a GPU HW context;
304the HW context is essentially (most of atleast) the state of a GPU.
305In addition to the ordering guarantees, the kernel will restore GPU
306state via HW context when commands are issued to a context, this saves
307user space the need to restore (most of atleast) the GPU state at the
308start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
309work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
310to identify what context to use with the command.
311
312The GPU has its own memory management and address space. The kernel
313driver maintains the memory translation table for the GPU. For older
314GPUs (i.e. those before Gen8), there is a single global such translation
315table, a global Graphics Translation Table (GTT). For newer generation
316GPUs each context has its own translation table, called Per-Process
317Graphics Translation Table (PPGTT). Of important note, is that although
318PPGTT is named per-process it is actually per context. When user space
319submits a batchbuffer, the kernel walks the list of GEM buffer objects
320used by the batchbuffer and guarantees that not only is the memory of
321each such GEM buffer object resident but it is also present in the
322(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
323then it is given an address. Two consequences of this are: the kernel
324needs to edit the batchbuffer submitted to write the correct value of
325the GPU address when a GEM BO is assigned a GPU address and the kernel
326might evict a different GEM BO from the (PP)GTT to make address room
327for another GEM BO. Consequently, the ioctls submitting a batchbuffer
328for execution also include a list of all locations within buffers that
329refer to GPU-addresses so that the kernel can edit the buffer correctly.
330This process is dubbed relocation.
331
332GEM BO Management Implementation Details
333----------------------------------------
334
335.. kernel-doc:: drivers/gpu/drm/i915/i915_vma.h
336 :doc: Virtual Memory Address
337
338Buffer Object Eviction
339----------------------
340
341This section documents the interface functions for evicting buffer
342objects to make space available in the virtual gpu address spaces. Note
343that this is mostly orthogonal to shrinking buffer objects caches, which
344has the goal to make main memory (shared with the gpu through the
345unified memory architecture) available.
346
347.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
348 :internal:
349
350Buffer Object Memory Shrinking
351------------------------------
352
353This section documents the interface function for shrinking memory usage
354of buffer object caches. Shrinking is used to make main memory
355available. Note that this is mostly orthogonal to evicting buffer
356objects, which has the goal to make space in gpu virtual address spaces.
357
8a6f43d4 358.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
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359 :internal:
360
ca00c2b9 361Batchbuffer Parsing
22554020 362-------------------
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363
364.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
365 :doc: batch buffer command parser
366
367.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
368 :internal:
369
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370User Batchbuffer Execution
371--------------------------
372
8a6f43d4 373.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
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374 :doc: User command execution
375
ca00c2b9 376Logical Rings, Logical Ring Contexts and Execlists
22554020 377--------------------------------------------------
ca00c2b9 378
bcc8737d 379.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c
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380 :doc: Logical Rings, Logical Ring Contexts and Execlists
381
ca00c2b9 382Global GTT views
22554020 383----------------
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384
385.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
386 :doc: Global GTT views
387
388.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
389 :internal:
390
391GTT Fences and Swizzling
22554020 392------------------------
ca00c2b9 393
ebc896db 394.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
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395 :internal:
396
397Global GTT Fence Handling
22554020 398~~~~~~~~~~~~~~~~~~~~~~~~~
ca00c2b9 399
ebc896db 400.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
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401 :doc: fence register handling
402
403Hardware Tiling and Swizzling Details
22554020 404~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ca00c2b9 405
ebc896db 406.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
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407 :doc: tiling swizzling details
408
409Object Tiling IOCTLs
22554020 410--------------------
ca00c2b9 411
8a6f43d4 412.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
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413 :internal:
414
8a6f43d4 415.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
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416 :doc: buffer object tiling
417
fbe6f8f2 418WOPCM
4072761b 419-----
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420
421WOPCM Layout
4072761b 422~~~~~~~~~~~~
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423
424.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c
425 :doc: WOPCM Layout
426
ca00c2b9 427GuC
4072761b 428---
ca00c2b9 429
199ddded 430Firmware Layout
4072761b 431~~~~~~~~~~~~~~~
199ddded 432
abf30f23 433.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
199ddded
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434 :doc: Firmware Layout
435
ca00c2b9 436GuC-specific firmware loader
4072761b 437~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ca00c2b9 438
dbbff8c3 439.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
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440 :internal:
441
442GuC-based command submission
4072761b 443~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ca00c2b9 444
dbbff8c3 445.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
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446 :doc: GuC-based command submission
447
dbbff8c3 448.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
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449 :internal:
450
fbe6f8f2 451GuC Address Space
4072761b 452~~~~~~~~~~~~~~~~~
fbe6f8f2 453
dbbff8c3 454.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
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455 :doc: GuC Address Space
456
ca00c2b9 457Tracing
22554020 458=======
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459
460This sections covers all things related to the tracepoints implemented
461in the i915 driver.
462
463i915_ppgtt_create and i915_ppgtt_release
22554020 464----------------------------------------
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465
466.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
467 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints
468
469i915_context_create and i915_context_free
22554020 470-----------------------------------------
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471
472.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
473 :doc: i915_context_create and i915_context_free tracepoints
474
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475Perf
476====
477
478Overview
479--------
480.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
481 :doc: i915 Perf Overview
482
483Comparison with Core Perf
484-------------------------
485.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
486 :doc: i915 Perf History and Comparison with Core Perf
487
488i915 Driver Entry Points
489------------------------
490
491This section covers the entrypoints exported outside of i915_perf.c to
492integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl.
493
494.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
495 :functions: i915_perf_init
496.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
497 :functions: i915_perf_fini
498.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
499 :functions: i915_perf_register
500.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
501 :functions: i915_perf_unregister
502.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
503 :functions: i915_perf_open_ioctl
504.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
505 :functions: i915_perf_release
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506.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
507 :functions: i915_perf_add_config_ioctl
508.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
509 :functions: i915_perf_remove_config_ioctl
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510
511i915 Perf Stream
512----------------
513
514This section covers the stream-semantics-agnostic structures and functions
515for representing an i915 perf stream FD and associated file operations.
516
517.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
518 :functions: i915_perf_stream
519.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
520 :functions: i915_perf_stream_ops
521
522.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
523 :functions: read_properties_unlocked
524.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
525 :functions: i915_perf_open_ioctl_locked
526.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
527 :functions: i915_perf_destroy_locked
528.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
529 :functions: i915_perf_read
530.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
531 :functions: i915_perf_ioctl
532.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
533 :functions: i915_perf_enable_locked
534.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
535 :functions: i915_perf_disable_locked
536.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
537 :functions: i915_perf_poll
538.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
539 :functions: i915_perf_poll_locked
540
541i915 Perf Observation Architecture Stream
542-----------------------------------------
543
544.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
545 :functions: i915_oa_ops
546
547.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
548 :functions: i915_oa_stream_init
549.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
550 :functions: i915_oa_read
551.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
552 :functions: i915_oa_stream_enable
553.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
554 :functions: i915_oa_stream_disable
555.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
556 :functions: i915_oa_wait_unlocked
557.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
558 :functions: i915_oa_poll_wait
559
560All i915 Perf Internals
561-----------------------
562
563This section simply includes all currently documented i915 perf internals, in
564no particular order, but may include some more minor utilities or platform
565specific details than found in the more high-level sections.
566
567.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
568 :internal:
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569
570Style
571=====
572
573The drm/i915 driver codebase has some style rules in addition to (and, in some
574cases, deviating from) the kernel coding style.
575
576Register macro definition style
577-------------------------------
578
579The style guide for ``i915_reg.h``.
580
581.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
582 :doc: The i915 register macro definition style guide