i2c: core: add device-managed version of i2c_new_dummy
[linux-2.6-block.git] / Documentation / driver-model / devres.txt
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1Devres - Managed Device Resource
2================================
3
4Tejun Heo <teheo@suse.de>
5
6First draft 10 January 2007
7
8
91. Intro : Huh? Devres?
102. Devres : Devres in a nutshell
113. Devres Group : Group devres'es and release them together
124. Details : Life time rules, calling context, ...
135. Overhead : How much do we have to pay for this?
146. List of managed interfaces : Currently implemented managed interfaces
15
16
17 1. Intro
18 --------
19
20devres came up while trying to convert libata to use iomap. Each
21iomapped address should be kept and unmapped on driver detach. For
22example, a plain SFF ATA controller (that is, good old PCI IDE) in
23native mode makes use of 5 PCI BARs and all of them should be
24maintained.
25
26As with many other device drivers, libata low level drivers have
27sufficient bugs in ->remove and ->probe failure path. Well, yes,
28that's probably because libata low level driver developers are lazy
29bunch, but aren't all low level driver developers? After spending a
30day fiddling with braindamaged hardware with no document or
31braindamaged document, if it's finally working, well, it's working.
32
33For one reason or another, low level drivers don't receive as much
34attention or testing as core code, and bugs on driver detach or
01dd2fbf 35initialization failure don't happen often enough to be noticeable.
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36Init failure path is worse because it's much less travelled while
37needs to handle multiple entry points.
38
39So, many low level drivers end up leaking resources on driver detach
40and having half broken failure path implementation in ->probe() which
41would leak resources or even cause oops when failure occurs. iomap
42adds more to this mix. So do msi and msix.
43
44
45 2. Devres
46 ---------
47
48devres is basically linked list of arbitrarily sized memory areas
49associated with a struct device. Each devres entry is associated with
50a release function. A devres can be released in several ways. No
51matter what, all devres entries are released on driver detach. On
52release, the associated release function is invoked and then the
53devres entry is freed.
54
55Managed interface is created for resources commonly used by device
56drivers using devres. For example, coherent DMA memory is acquired
57using dma_alloc_coherent(). The managed version is called
58dmam_alloc_coherent(). It is identical to dma_alloc_coherent() except
59for the DMA memory allocated using it is managed and will be
60automatically released on driver detach. Implementation looks like
61the following.
62
63 struct dma_devres {
64 size_t size;
65 void *vaddr;
66 dma_addr_t dma_handle;
67 };
68
69 static void dmam_coherent_release(struct device *dev, void *res)
70 {
71 struct dma_devres *this = res;
72
73 dma_free_coherent(dev, this->size, this->vaddr, this->dma_handle);
74 }
75
76 dmam_alloc_coherent(dev, size, dma_handle, gfp)
77 {
78 struct dma_devres *dr;
79 void *vaddr;
80
81 dr = devres_alloc(dmam_coherent_release, sizeof(*dr), gfp);
82 ...
83
84 /* alloc DMA memory as usual */
85 vaddr = dma_alloc_coherent(...);
86 ...
87
88 /* record size, vaddr, dma_handle in dr */
89 dr->vaddr = vaddr;
90 ...
91
92 devres_add(dev, dr);
93
94 return vaddr;
95 }
96
97If a driver uses dmam_alloc_coherent(), the area is guaranteed to be
98freed whether initialization fails half-way or the device gets
99detached. If most resources are acquired using managed interface, a
100driver can have much simpler init and exit code. Init path basically
101looks like the following.
102
103 my_init_one()
104 {
105 struct mydev *d;
106
107 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
108 if (!d)
109 return -ENOMEM;
110
111 d->ring = dmam_alloc_coherent(...);
112 if (!d->ring)
113 return -ENOMEM;
114
115 if (check something)
116 return -EINVAL;
117 ...
118
119 return register_to_upper_layer(d);
120 }
121
122And exit path,
123
124 my_remove_one()
125 {
126 unregister_from_upper_layer(d);
127 shutdown_my_hardware();
128 }
129
130As shown above, low level drivers can be simplified a lot by using
131devres. Complexity is shifted from less maintained low level drivers
132to better maintained higher layer. Also, as init failure path is
133shared with exit path, both can get more testing.
134
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135Note though that when converting current calls or assignments to
136managed devm_* versions it is up to you to check if internal operations
137like allocating memory, have failed. Managed resources pertains to the
138freeing of these resources *only* - all other checks needed are still
139on you. In some cases this may mean introducing checks that were not
140necessary before moving to the managed devm_* calls.
141
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142
143 3. Devres group
144 ---------------
145
146Devres entries can be grouped using devres group. When a group is
147released, all contained normal devres entries and properly nested
148groups are released. One usage is to rollback series of acquired
149resources on failure. For example,
150
151 if (!devres_open_group(dev, NULL, GFP_KERNEL))
152 return -ENOMEM;
153
154 acquire A;
155 if (failed)
156 goto err;
157
158 acquire B;
159 if (failed)
160 goto err;
161 ...
162
163 devres_remove_group(dev, NULL);
164 return 0;
165
166 err:
167 devres_release_group(dev, NULL);
168 return err_code;
169
01dd2fbf 170As resource acquisition failure usually means probe failure, constructs
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171like above are usually useful in midlayer driver (e.g. libata core
172layer) where interface function shouldn't have side effect on failure.
173For LLDs, just returning error code suffices in most cases.
174
175Each group is identified by void *id. It can either be explicitly
176specified by @id argument to devres_open_group() or automatically
177created by passing NULL as @id as in the above example. In both
178cases, devres_open_group() returns the group's id. The returned id
179can be passed to other devres functions to select the target group.
180If NULL is given to those functions, the latest open group is
181selected.
182
183For example, you can do something like the following.
184
185 int my_midlayer_create_something()
186 {
187 if (!devres_open_group(dev, my_midlayer_create_something, GFP_KERNEL))
188 return -ENOMEM;
189
190 ...
191
3265b545 192 devres_close_group(dev, my_midlayer_create_something);
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193 return 0;
194 }
195
196 void my_midlayer_destroy_something()
197 {
19f59460 198 devres_release_group(dev, my_midlayer_create_something);
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199 }
200
201
202 4. Details
203 ----------
204
205Lifetime of a devres entry begins on devres allocation and finishes
206when it is released or destroyed (removed and freed) - no reference
207counting.
208
209devres core guarantees atomicity to all basic devres operations and
210has support for single-instance devres types (atomic
211lookup-and-add-if-not-found). Other than that, synchronizing
212concurrent accesses to allocated devres data is caller's
213responsibility. This is usually non-issue because bus ops and
214resource allocations already do the job.
215
216For an example of single-instance devres type, read pcim_iomap_table()
2c19c49a 217in lib/devres.c.
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218
219All devres interface functions can be called without context if the
220right gfp mask is given.
221
222
223 5. Overhead
224 -----------
225
226Each devres bookkeeping info is allocated together with requested data
227area. With debug option turned off, bookkeeping info occupies 16
228bytes on 32bit machines and 24 bytes on 64bit (three pointers rounded
229up to ull alignment). If singly linked list is used, it can be
230reduced to two pointers (8 bytes on 32bit, 16 bytes on 64bit).
231
232Each devres group occupies 8 pointers. It can be reduced to 6 if
233singly linked list is used.
234
235Memory space overhead on ahci controller with two ports is between 300
236and 400 bytes on 32bit machine after naive conversion (we can
237certainly invest a bit more effort into libata core layer).
238
239
240 6. List of managed interfaces
241 -----------------------------
242
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243CLOCK
244 devm_clk_get()
60b8f0dd 245 devm_clk_get_optional()
d8e1e012 246 devm_clk_put()
4143804c 247 devm_clk_hw_register()
aa795c41 248 devm_of_clk_add_hw_provider()
3eee6c7d 249 devm_clk_hw_register_clkdev()
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250
251DMA
f39b948d 252 dmaenginem_async_device_register()
d8e1e012 253 dmam_alloc_coherent()
63d36c95 254 dmam_alloc_attrs()
d8e1e012 255 dmam_free_coherent()
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256 dmam_pool_create()
257 dmam_pool_destroy()
258
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259DRM
260 devm_drm_dev_init()
261
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262GPIO
263 devm_gpiod_get()
264 devm_gpiod_get_index()
265 devm_gpiod_get_index_optional()
266 devm_gpiod_get_optional()
267 devm_gpiod_put()
891ddbc7 268 devm_gpiod_unhinge()
38115ead 269 devm_gpiochip_add_data()
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270 devm_gpio_request()
271 devm_gpio_request_one()
272 devm_gpio_free()
543f43ce 273
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274I2C
275 devm_i2c_new_dummy_device()
276
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277IIO
278 devm_iio_device_alloc()
279 devm_iio_device_free()
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280 devm_iio_device_register()
281 devm_iio_device_unregister()
780103fe
KW
282 devm_iio_kfifo_allocate()
283 devm_iio_kfifo_free()
70e48348
GB
284 devm_iio_triggered_buffer_setup()
285 devm_iio_triggered_buffer_cleanup()
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286 devm_iio_trigger_alloc()
287 devm_iio_trigger_free()
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288 devm_iio_trigger_register()
289 devm_iio_trigger_unregister()
e21a294d
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290 devm_iio_channel_get()
291 devm_iio_channel_release()
292 devm_iio_channel_get_all()
293 devm_iio_channel_release_all()
224b995a 294
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295INPUT
296 devm_input_allocate_device()
297
9ac7849e 298IO region
9ac7849e 299 devm_release_mem_region()
d8e1e012 300 devm_release_region()
8d38821c 301 devm_release_resource()
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302 devm_request_mem_region()
303 devm_request_region()
8d38821c 304 devm_request_resource()
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305
306IOMAP
307 devm_ioport_map()
308 devm_ioport_unmap()
309 devm_ioremap()
310 devm_ioremap_nocache()
34644524 311 devm_ioremap_wc()
75096579 312 devm_ioremap_resource() : checks resource, requests memory region, ioremaps
d8e1e012 313 devm_iounmap()
9ac7849e 314 pcim_iomap()
9ac7849e 315 pcim_iomap_regions() : do request_region() and iomap() on multiple BARs
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316 pcim_iomap_table() : array of mapped addresses indexed by BAR
317 pcim_iounmap()
070b9079 318
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319IRQ
320 devm_free_irq()
ea05166a 321 devm_request_any_context_irq()
d8e1e012 322 devm_request_irq()
ea05166a 323 devm_request_threaded_irq()
2b5e7730
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324 devm_irq_alloc_descs()
325 devm_irq_alloc_desc()
326 devm_irq_alloc_desc_at()
327 devm_irq_alloc_desc_from()
328 devm_irq_alloc_descs_from()
1c3e3630 329 devm_irq_alloc_generic_chip()
30fd8fc5 330 devm_irq_setup_generic_chip()
44e72c7e 331 devm_irq_sim_init()
a8a97db9 332
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333LED
334 devm_led_classdev_register()
335 devm_led_classdev_unregister()
336
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337MDIO
338 devm_mdiobus_alloc()
339 devm_mdiobus_alloc_size()
340 devm_mdiobus_free()
341
342MEM
343 devm_free_pages()
344 devm_get_free_pages()
bef59c50 345 devm_kasprintf()
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346 devm_kcalloc()
347 devm_kfree()
348 devm_kmalloc()
349 devm_kmalloc_array()
350 devm_kmemdup()
54270354 351 devm_kstrdup()
bef59c50 352 devm_kvasprintf()
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353 devm_kzalloc()
354
3698283b 355MFD
b594b101 356 devm_mfd_add_devices()
3698283b 357
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358MUX
359 devm_mux_chip_alloc()
360 devm_mux_chip_register()
361 devm_mux_control_get()
3698283b 362
ff86aae3
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363PER-CPU MEM
364 devm_alloc_percpu()
365 devm_free_percpu()
366
d8e1e012 367PCI
5c3f18cc 368 devm_pci_alloc_host_bridge() : managed PCI host bridge allocation
490cb6dd
LP
369 devm_pci_remap_cfgspace() : ioremap PCI configuration space
370 devm_pci_remap_cfg_resource() : ioremap PCI configuration space resource
371 pcim_enable_device() : after success, all PCI ops become managed
372 pcim_pin_device() : keep PCI device enabled after release
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373
374PHY
375 devm_usb_get_phy()
376 devm_usb_put_phy()
3d1482fe 377
6d4ca1fb
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378PINCTRL
379 devm_pinctrl_get()
380 devm_pinctrl_put()
1f8dd72f
LD
381 devm_pinctrl_register()
382 devm_pinctrl_unregister()
6354316d 383
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384POWER
385 devm_reboot_mode_register()
386 devm_reboot_mode_unregister()
387
6354316d
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388PWM
389 devm_pwm_get()
390 devm_pwm_put()
2202d4e8 391
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392REGULATOR
393 devm_regulator_bulk_get()
394 devm_regulator_get()
395 devm_regulator_put()
396 devm_regulator_register()
0244d84f 397
8d5b5d5c
MY
398RESET
399 devm_reset_control_get()
400 devm_reset_controller_register()
401
2cb67d20
AS
402SERDEV
403 devm_serdev_device_open()
404
0244d84f
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405SLAVE DMA ENGINE
406 devm_acpi_dma_controller_register()
666d5b4c
MB
407
408SPI
409 devm_spi_register_master()
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410
411WATCHDOG
412 devm_watchdog_register_device()