Documentation: devres: note checking needs when converting
[linux-2.6-block.git] / Documentation / driver-model / devres.txt
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1Devres - Managed Device Resource
2================================
3
4Tejun Heo <teheo@suse.de>
5
6First draft 10 January 2007
7
8
91. Intro : Huh? Devres?
102. Devres : Devres in a nutshell
113. Devres Group : Group devres'es and release them together
124. Details : Life time rules, calling context, ...
135. Overhead : How much do we have to pay for this?
146. List of managed interfaces : Currently implemented managed interfaces
15
16
17 1. Intro
18 --------
19
20devres came up while trying to convert libata to use iomap. Each
21iomapped address should be kept and unmapped on driver detach. For
22example, a plain SFF ATA controller (that is, good old PCI IDE) in
23native mode makes use of 5 PCI BARs and all of them should be
24maintained.
25
26As with many other device drivers, libata low level drivers have
27sufficient bugs in ->remove and ->probe failure path. Well, yes,
28that's probably because libata low level driver developers are lazy
29bunch, but aren't all low level driver developers? After spending a
30day fiddling with braindamaged hardware with no document or
31braindamaged document, if it's finally working, well, it's working.
32
33For one reason or another, low level drivers don't receive as much
34attention or testing as core code, and bugs on driver detach or
01dd2fbf 35initialization failure don't happen often enough to be noticeable.
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36Init failure path is worse because it's much less travelled while
37needs to handle multiple entry points.
38
39So, many low level drivers end up leaking resources on driver detach
40and having half broken failure path implementation in ->probe() which
41would leak resources or even cause oops when failure occurs. iomap
42adds more to this mix. So do msi and msix.
43
44
45 2. Devres
46 ---------
47
48devres is basically linked list of arbitrarily sized memory areas
49associated with a struct device. Each devres entry is associated with
50a release function. A devres can be released in several ways. No
51matter what, all devres entries are released on driver detach. On
52release, the associated release function is invoked and then the
53devres entry is freed.
54
55Managed interface is created for resources commonly used by device
56drivers using devres. For example, coherent DMA memory is acquired
57using dma_alloc_coherent(). The managed version is called
58dmam_alloc_coherent(). It is identical to dma_alloc_coherent() except
59for the DMA memory allocated using it is managed and will be
60automatically released on driver detach. Implementation looks like
61the following.
62
63 struct dma_devres {
64 size_t size;
65 void *vaddr;
66 dma_addr_t dma_handle;
67 };
68
69 static void dmam_coherent_release(struct device *dev, void *res)
70 {
71 struct dma_devres *this = res;
72
73 dma_free_coherent(dev, this->size, this->vaddr, this->dma_handle);
74 }
75
76 dmam_alloc_coherent(dev, size, dma_handle, gfp)
77 {
78 struct dma_devres *dr;
79 void *vaddr;
80
81 dr = devres_alloc(dmam_coherent_release, sizeof(*dr), gfp);
82 ...
83
84 /* alloc DMA memory as usual */
85 vaddr = dma_alloc_coherent(...);
86 ...
87
88 /* record size, vaddr, dma_handle in dr */
89 dr->vaddr = vaddr;
90 ...
91
92 devres_add(dev, dr);
93
94 return vaddr;
95 }
96
97If a driver uses dmam_alloc_coherent(), the area is guaranteed to be
98freed whether initialization fails half-way or the device gets
99detached. If most resources are acquired using managed interface, a
100driver can have much simpler init and exit code. Init path basically
101looks like the following.
102
103 my_init_one()
104 {
105 struct mydev *d;
106
107 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
108 if (!d)
109 return -ENOMEM;
110
111 d->ring = dmam_alloc_coherent(...);
112 if (!d->ring)
113 return -ENOMEM;
114
115 if (check something)
116 return -EINVAL;
117 ...
118
119 return register_to_upper_layer(d);
120 }
121
122And exit path,
123
124 my_remove_one()
125 {
126 unregister_from_upper_layer(d);
127 shutdown_my_hardware();
128 }
129
130As shown above, low level drivers can be simplified a lot by using
131devres. Complexity is shifted from less maintained low level drivers
132to better maintained higher layer. Also, as init failure path is
133shared with exit path, both can get more testing.
134
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135Note though that when converting current calls or assignments to
136managed devm_* versions it is up to you to check if internal operations
137like allocating memory, have failed. Managed resources pertains to the
138freeing of these resources *only* - all other checks needed are still
139on you. In some cases this may mean introducing checks that were not
140necessary before moving to the managed devm_* calls.
141
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142
143 3. Devres group
144 ---------------
145
146Devres entries can be grouped using devres group. When a group is
147released, all contained normal devres entries and properly nested
148groups are released. One usage is to rollback series of acquired
149resources on failure. For example,
150
151 if (!devres_open_group(dev, NULL, GFP_KERNEL))
152 return -ENOMEM;
153
154 acquire A;
155 if (failed)
156 goto err;
157
158 acquire B;
159 if (failed)
160 goto err;
161 ...
162
163 devres_remove_group(dev, NULL);
164 return 0;
165
166 err:
167 devres_release_group(dev, NULL);
168 return err_code;
169
01dd2fbf 170As resource acquisition failure usually means probe failure, constructs
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171like above are usually useful in midlayer driver (e.g. libata core
172layer) where interface function shouldn't have side effect on failure.
173For LLDs, just returning error code suffices in most cases.
174
175Each group is identified by void *id. It can either be explicitly
176specified by @id argument to devres_open_group() or automatically
177created by passing NULL as @id as in the above example. In both
178cases, devres_open_group() returns the group's id. The returned id
179can be passed to other devres functions to select the target group.
180If NULL is given to those functions, the latest open group is
181selected.
182
183For example, you can do something like the following.
184
185 int my_midlayer_create_something()
186 {
187 if (!devres_open_group(dev, my_midlayer_create_something, GFP_KERNEL))
188 return -ENOMEM;
189
190 ...
191
3265b545 192 devres_close_group(dev, my_midlayer_create_something);
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193 return 0;
194 }
195
196 void my_midlayer_destroy_something()
197 {
19f59460 198 devres_release_group(dev, my_midlayer_create_something);
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199 }
200
201
202 4. Details
203 ----------
204
205Lifetime of a devres entry begins on devres allocation and finishes
206when it is released or destroyed (removed and freed) - no reference
207counting.
208
209devres core guarantees atomicity to all basic devres operations and
210has support for single-instance devres types (atomic
211lookup-and-add-if-not-found). Other than that, synchronizing
212concurrent accesses to allocated devres data is caller's
213responsibility. This is usually non-issue because bus ops and
214resource allocations already do the job.
215
216For an example of single-instance devres type, read pcim_iomap_table()
2c19c49a 217in lib/devres.c.
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218
219All devres interface functions can be called without context if the
220right gfp mask is given.
221
222
223 5. Overhead
224 -----------
225
226Each devres bookkeeping info is allocated together with requested data
227area. With debug option turned off, bookkeeping info occupies 16
228bytes on 32bit machines and 24 bytes on 64bit (three pointers rounded
229up to ull alignment). If singly linked list is used, it can be
230reduced to two pointers (8 bytes on 32bit, 16 bytes on 64bit).
231
232Each devres group occupies 8 pointers. It can be reduced to 6 if
233singly linked list is used.
234
235Memory space overhead on ahci controller with two ports is between 300
236and 400 bytes on 32bit machine after naive conversion (we can
237certainly invest a bit more effort into libata core layer).
238
239
240 6. List of managed interfaces
241 -----------------------------
242
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243CLOCK
244 devm_clk_get()
245 devm_clk_put()
4143804c 246 devm_clk_hw_register()
aa795c41 247 devm_of_clk_add_hw_provider()
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248
249DMA
f39b948d 250 dmaenginem_async_device_register()
d8e1e012 251 dmam_alloc_coherent()
63d36c95 252 dmam_alloc_attrs()
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253 dmam_declare_coherent_memory()
254 dmam_free_coherent()
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255 dmam_pool_create()
256 dmam_pool_destroy()
257
258GPIO
259 devm_gpiod_get()
260 devm_gpiod_get_index()
261 devm_gpiod_get_index_optional()
262 devm_gpiod_get_optional()
263 devm_gpiod_put()
38115ead
LD
264 devm_gpiochip_add_data()
265 devm_gpiochip_remove()
77ae582c
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266 devm_gpio_request()
267 devm_gpio_request_one()
268 devm_gpio_free()
543f43ce 269
224b995a
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270IIO
271 devm_iio_device_alloc()
272 devm_iio_device_free()
8caa07c0
SK
273 devm_iio_device_register()
274 devm_iio_device_unregister()
780103fe
KW
275 devm_iio_kfifo_allocate()
276 devm_iio_kfifo_free()
70e48348
GB
277 devm_iio_triggered_buffer_setup()
278 devm_iio_triggered_buffer_cleanup()
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279 devm_iio_trigger_alloc()
280 devm_iio_trigger_free()
9083325f
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281 devm_iio_trigger_register()
282 devm_iio_trigger_unregister()
e21a294d
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283 devm_iio_channel_get()
284 devm_iio_channel_release()
285 devm_iio_channel_get_all()
286 devm_iio_channel_release_all()
224b995a 287
2ea2dc87
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288INPUT
289 devm_input_allocate_device()
290
9ac7849e 291IO region
9ac7849e 292 devm_release_mem_region()
d8e1e012 293 devm_release_region()
8d38821c 294 devm_release_resource()
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295 devm_request_mem_region()
296 devm_request_region()
8d38821c 297 devm_request_resource()
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298
299IOMAP
300 devm_ioport_map()
301 devm_ioport_unmap()
302 devm_ioremap()
303 devm_ioremap_nocache()
34644524 304 devm_ioremap_wc()
75096579 305 devm_ioremap_resource() : checks resource, requests memory region, ioremaps
d8e1e012 306 devm_iounmap()
9ac7849e 307 pcim_iomap()
9ac7849e 308 pcim_iomap_regions() : do request_region() and iomap() on multiple BARs
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309 pcim_iomap_table() : array of mapped addresses indexed by BAR
310 pcim_iounmap()
070b9079 311
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312IRQ
313 devm_free_irq()
ea05166a 314 devm_request_any_context_irq()
d8e1e012 315 devm_request_irq()
ea05166a 316 devm_request_threaded_irq()
2b5e7730
BG
317 devm_irq_alloc_descs()
318 devm_irq_alloc_desc()
319 devm_irq_alloc_desc_at()
320 devm_irq_alloc_desc_from()
321 devm_irq_alloc_descs_from()
1c3e3630 322 devm_irq_alloc_generic_chip()
30fd8fc5 323 devm_irq_setup_generic_chip()
44e72c7e 324 devm_irq_sim_init()
a8a97db9 325
ca1bb4ee
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326LED
327 devm_led_classdev_register()
328 devm_led_classdev_unregister()
329
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330MDIO
331 devm_mdiobus_alloc()
332 devm_mdiobus_alloc_size()
333 devm_mdiobus_free()
334
335MEM
336 devm_free_pages()
337 devm_get_free_pages()
bef59c50 338 devm_kasprintf()
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339 devm_kcalloc()
340 devm_kfree()
341 devm_kmalloc()
342 devm_kmalloc_array()
343 devm_kmemdup()
54270354 344 devm_kstrdup()
bef59c50 345 devm_kvasprintf()
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346 devm_kzalloc()
347
3698283b 348MFD
b594b101 349 devm_mfd_add_devices()
3698283b 350
a3b02a9c
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351MUX
352 devm_mux_chip_alloc()
353 devm_mux_chip_register()
354 devm_mux_control_get()
3698283b 355
ff86aae3
MB
356PER-CPU MEM
357 devm_alloc_percpu()
358 devm_free_percpu()
359
d8e1e012 360PCI
5c3f18cc 361 devm_pci_alloc_host_bridge() : managed PCI host bridge allocation
490cb6dd
LP
362 devm_pci_remap_cfgspace() : ioremap PCI configuration space
363 devm_pci_remap_cfg_resource() : ioremap PCI configuration space resource
364 pcim_enable_device() : after success, all PCI ops become managed
365 pcim_pin_device() : keep PCI device enabled after release
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366
367PHY
368 devm_usb_get_phy()
369 devm_usb_put_phy()
3d1482fe 370
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371PINCTRL
372 devm_pinctrl_get()
373 devm_pinctrl_put()
1f8dd72f
LD
374 devm_pinctrl_register()
375 devm_pinctrl_unregister()
6354316d 376
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377POWER
378 devm_reboot_mode_register()
379 devm_reboot_mode_unregister()
380
6354316d
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381PWM
382 devm_pwm_get()
383 devm_pwm_put()
2202d4e8 384
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385REGULATOR
386 devm_regulator_bulk_get()
387 devm_regulator_get()
388 devm_regulator_put()
389 devm_regulator_register()
0244d84f 390
8d5b5d5c
MY
391RESET
392 devm_reset_control_get()
393 devm_reset_controller_register()
394
2cb67d20
AS
395SERDEV
396 devm_serdev_device_open()
397
0244d84f
AS
398SLAVE DMA ENGINE
399 devm_acpi_dma_controller_register()
666d5b4c
MB
400
401SPI
402 devm_spi_register_master()
83fbae5a
NA
403
404WATCHDOG
405 devm_watchdog_register_device()