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652a49bc | 1 | .. SPDX-License-Identifier: GPL-2.0 |
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2 | |
3 | ======================================== | |
4 | GPMC (General Purpose Memory Controller) | |
5 | ======================================== | |
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6 | |
7 | GPMC is an unified memory controller dedicated to interfacing external | |
8 | memory devices like | |
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10 | * Asynchronous SRAM like memories and application specific integrated |
11 | circuit devices. | |
12 | * Asynchronous, synchronous, and page mode burst NOR flash devices | |
13 | NAND flash | |
14 | * Pseudo-SRAM devices | |
15 | ||
16 | GPMC is found on Texas Instruments SoC's (OMAP based) | |
d3603f4c | 17 | IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1 |
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18 | |
19 | ||
20 | GPMC generic timing calculation: | |
21 | ================================ | |
22 | ||
23 | GPMC has certain timings that has to be programmed for proper | |
24 | functioning of the peripheral, while peripheral has another set of | |
25 | timings. To have peripheral work with gpmc, peripheral timings has to | |
26 | be translated to the form gpmc can understand. The way it has to be | |
27 | translated depends on the connected peripheral. Also there is a | |
28 | dependency for certain gpmc timings on gpmc clock frequency. Hence a | |
29 | generic timing routine was developed to achieve above requirements. | |
30 | ||
31 | Generic routine provides a generic method to calculate gpmc timings | |
32 | from gpmc peripheral timings. struct gpmc_device_timings fields has to | |
33 | be updated with timings from the datasheet of the peripheral that is | |
34 | connected to gpmc. A few of the peripheral timings can be fed either | |
35 | in time or in cycles, provision to handle this scenario has been | |
36 | provided (refer struct gpmc_device_timings definition). It may so | |
37 | happen that timing as specified by peripheral datasheet is not present | |
38 | in timing structure, in this scenario, try to correlate peripheral | |
39 | timing to the one available. If that doesn't work, try to add a new | |
40 | field as required by peripheral, educate generic timing routine to | |
41 | handle it, make sure that it does not break any of the existing. | |
42 | Then there may be cases where peripheral datasheet doesn't mention | |
43 | certain fields of struct gpmc_device_timings, zero those entries. | |
44 | ||
45 | Generic timing routine has been verified to work properly on | |
46 | multiple onenand's and tusb6010 peripherals. | |
47 | ||
48 | A word of caution: generic timing routine has been developed based | |
49 | on understanding of gpmc timings, peripheral timings, available | |
50 | custom timing routines, a kind of reverse engineering without | |
51 | most of the datasheets & hardware (to be exact none of those supported | |
52 | in mainline having custom timing routine) and by simulation. | |
53 | ||
54 | gpmc timing dependency on peripheral timings: | |
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56 | [<gpmc_timing>: <peripheral timing1>, <peripheral timing2> ...] |
57 | ||
58 | 1. common | |
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59 | |
60 | cs_on: | |
61 | t_ceasu | |
62 | adv_on: | |
63 | t_avdasu, t_ceavd | |
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64 | |
65 | 2. sync common | |
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66 | |
67 | sync_clk: | |
68 | clk | |
69 | page_burst_access: | |
70 | t_bacc | |
71 | clk_activation: | |
72 | t_ces, t_avds | |
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73 | |
74 | 3. read async muxed | |
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75 | |
76 | adv_rd_off: | |
77 | t_avdp_r | |
78 | oe_on: | |
79 | t_oeasu, t_aavdh | |
80 | access: | |
81 | t_iaa, t_oe, t_ce, t_aa | |
82 | rd_cycle: | |
83 | t_rd_cycle, t_cez_r, t_oez | |
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84 | |
85 | 4. read async non-muxed | |
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86 | |
87 | adv_rd_off: | |
88 | t_avdp_r | |
89 | oe_on: | |
90 | t_oeasu | |
91 | access: | |
92 | t_iaa, t_oe, t_ce, t_aa | |
93 | rd_cycle: | |
94 | t_rd_cycle, t_cez_r, t_oez | |
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95 | |
96 | 5. read sync muxed | |
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97 | |
98 | adv_rd_off: | |
99 | t_avdp_r, t_avdh | |
100 | oe_on: | |
101 | t_oeasu, t_ach, cyc_aavdh_oe | |
102 | access: | |
103 | t_iaa, cyc_iaa, cyc_oe | |
104 | rd_cycle: | |
105 | t_cez_r, t_oez, t_ce_rdyz | |
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106 | |
107 | 6. read sync non-muxed | |
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108 | |
109 | adv_rd_off: | |
110 | t_avdp_r | |
111 | oe_on: | |
112 | t_oeasu | |
113 | access: | |
114 | t_iaa, cyc_iaa, cyc_oe | |
115 | rd_cycle: | |
116 | t_cez_r, t_oez, t_ce_rdyz | |
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117 | |
118 | 7. write async muxed | |
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119 | |
120 | adv_wr_off: | |
121 | t_avdp_w | |
122 | we_on, wr_data_mux_bus: | |
123 | t_weasu, t_aavdh, cyc_aavhd_we | |
124 | we_off: | |
125 | t_wpl | |
126 | cs_wr_off: | |
127 | t_wph | |
128 | wr_cycle: | |
129 | t_cez_w, t_wr_cycle | |
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130 | |
131 | 8. write async non-muxed | |
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132 | |
133 | adv_wr_off: | |
134 | t_avdp_w | |
135 | we_on, wr_data_mux_bus: | |
136 | t_weasu | |
137 | we_off: | |
138 | t_wpl | |
139 | cs_wr_off: | |
140 | t_wph | |
141 | wr_cycle: | |
142 | t_cez_w, t_wr_cycle | |
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143 | |
144 | 9. write sync muxed | |
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145 | |
146 | adv_wr_off: | |
147 | t_avdp_w, t_avdh | |
148 | we_on, wr_data_mux_bus: | |
149 | t_weasu, t_rdyo, t_aavdh, cyc_aavhd_we | |
150 | we_off: | |
151 | t_wpl, cyc_wpl | |
152 | cs_wr_off: | |
153 | t_wph | |
154 | wr_cycle: | |
155 | t_cez_w, t_ce_rdyz | |
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156 | |
157 | 10. write sync non-muxed | |
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158 | |
159 | adv_wr_off: | |
160 | t_avdp_w | |
161 | we_on, wr_data_mux_bus: | |
162 | t_weasu, t_rdyo | |
163 | we_off: | |
164 | t_wpl, cyc_wpl | |
165 | cs_wr_off: | |
166 | t_wph | |
167 | wr_cycle: | |
168 | t_cez_w, t_ce_rdyz | |
169 | ||
170 | ||
171 | Note: | |
172 | Many of gpmc timings are dependent on other gpmc timings (a few | |
173 | gpmc timings purely dependent on other gpmc timings, a reason that | |
174 | some of the gpmc timings are missing above), and it will result in | |
175 | indirect dependency of peripheral timings to gpmc timings other than | |
176 | mentioned above, refer timing routine for more details. To know what | |
177 | these peripheral timings correspond to, please see explanations in | |
178 | struct gpmc_device_timings definition. And for gpmc timings refer | |
179 | IP details (link above). |