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462c5c0a KK |
1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
7 | title: Qualcomm Universal Flash Storage (UFS) Controller | |
8 | ||
9 | maintainers: | |
10 | - Bjorn Andersson <bjorn.andersson@linaro.org> | |
11 | - Andy Gross <agross@kernel.org> | |
12 | ||
13 | # Select only our matches, not all jedec,ufs-2.0 | |
14 | select: | |
15 | properties: | |
16 | compatible: | |
17 | contains: | |
18 | const: qcom,ufshc | |
19 | required: | |
20 | - compatible | |
21 | ||
22 | properties: | |
23 | compatible: | |
24 | items: | |
25 | - enum: | |
26 | - qcom,msm8994-ufshc | |
27 | - qcom,msm8996-ufshc | |
28 | - qcom,msm8998-ufshc | |
8f0c17bf | 29 | - qcom,sa8775p-ufshc |
7fb5aafc | 30 | - qcom,sc7180-ufshc |
98bfeda3 | 31 | - qcom,sc7280-ufshc |
ad91c1d7 | 32 | - qcom,sc8180x-ufshc |
2f3b3200 | 33 | - qcom,sc8280xp-ufshc |
462c5c0a | 34 | - qcom,sdm845-ufshc |
a11eaed3 | 35 | - qcom,sm6115-ufshc |
b5237d0b | 36 | - qcom,sm6125-ufshc |
3d8fa7a2 | 37 | - qcom,sm6350-ufshc |
462c5c0a KK |
38 | - qcom,sm8150-ufshc |
39 | - qcom,sm8250-ufshc | |
40 | - qcom,sm8350-ufshc | |
41 | - qcom,sm8450-ufshc | |
b8c20389 | 42 | - qcom,sm8550-ufshc |
e439e4a6 | 43 | - qcom,sm8650-ufshc |
462c5c0a KK |
44 | - const: qcom,ufshc |
45 | - const: jedec,ufs-2.0 | |
46 | ||
47 | clocks: | |
7fb5aafc | 48 | minItems: 7 |
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49 | maxItems: 11 |
50 | ||
51 | clock-names: | |
7fb5aafc | 52 | minItems: 7 |
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53 | maxItems: 11 |
54 | ||
85e182b4 JH |
55 | dma-coherent: true |
56 | ||
462c5c0a KK |
57 | interconnects: |
58 | minItems: 2 | |
59 | maxItems: 2 | |
60 | ||
61 | interconnect-names: | |
62 | items: | |
63 | - const: ufs-ddr | |
64 | - const: cpu-ufs | |
65 | ||
66 | iommus: | |
67 | minItems: 1 | |
68 | maxItems: 2 | |
69 | ||
70 | phys: | |
71 | maxItems: 1 | |
72 | ||
73 | phy-names: | |
74 | items: | |
75 | - const: ufsphy | |
76 | ||
77 | power-domains: | |
78 | maxItems: 1 | |
79 | ||
29a6d121 AV |
80 | qcom,ice: |
81 | $ref: /schemas/types.yaml#/definitions/phandle | |
82 | description: phandle to the Inline Crypto Engine node | |
83 | ||
462c5c0a KK |
84 | reg: |
85 | minItems: 1 | |
86 | maxItems: 2 | |
87 | ||
7839d566 LW |
88 | reg-names: |
89 | items: | |
90 | - const: std | |
91 | - const: ice | |
92 | ||
8ffbaa98 KK |
93 | required-opps: |
94 | maxItems: 1 | |
95 | ||
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96 | resets: |
97 | maxItems: 1 | |
98 | ||
99 | '#reset-cells': | |
100 | const: 1 | |
101 | ||
102 | reset-names: | |
103 | items: | |
104 | - const: rst | |
105 | ||
106 | reset-gpios: | |
107 | maxItems: 1 | |
108 | description: | |
109 | GPIO connected to the RESET pin of the UFS memory device. | |
110 | ||
111 | required: | |
112 | - compatible | |
113 | - reg | |
114 | ||
115 | allOf: | |
116 | - $ref: ufs-common.yaml | |
117 | ||
7fb5aafc KK |
118 | - if: |
119 | properties: | |
120 | compatible: | |
121 | contains: | |
122 | enum: | |
123 | - qcom,sc7180-ufshc | |
124 | then: | |
125 | properties: | |
126 | clocks: | |
127 | minItems: 7 | |
128 | maxItems: 7 | |
129 | clock-names: | |
130 | items: | |
131 | - const: core_clk | |
132 | - const: bus_aggr_clk | |
133 | - const: iface_clk | |
134 | - const: core_clk_unipro | |
135 | - const: ref_clk | |
136 | - const: tx_lane0_sync_clk | |
137 | - const: rx_lane0_sync_clk | |
138 | reg: | |
139 | maxItems: 1 | |
140 | reg-names: | |
141 | maxItems: 1 | |
142 | ||
462c5c0a KK |
143 | - if: |
144 | properties: | |
145 | compatible: | |
146 | contains: | |
147 | enum: | |
148 | - qcom,msm8998-ufshc | |
8f0c17bf | 149 | - qcom,sa8775p-ufshc |
98bfeda3 | 150 | - qcom,sc7280-ufshc |
ad91c1d7 | 151 | - qcom,sc8180x-ufshc |
2f3b3200 | 152 | - qcom,sc8280xp-ufshc |
462c5c0a KK |
153 | - qcom,sm8250-ufshc |
154 | - qcom,sm8350-ufshc | |
155 | - qcom,sm8450-ufshc | |
b8c20389 | 156 | - qcom,sm8550-ufshc |
e439e4a6 | 157 | - qcom,sm8650-ufshc |
462c5c0a KK |
158 | then: |
159 | properties: | |
160 | clocks: | |
161 | minItems: 8 | |
162 | maxItems: 8 | |
163 | clock-names: | |
164 | items: | |
165 | - const: core_clk | |
166 | - const: bus_aggr_clk | |
167 | - const: iface_clk | |
168 | - const: core_clk_unipro | |
169 | - const: ref_clk | |
170 | - const: tx_lane0_sync_clk | |
171 | - const: rx_lane0_sync_clk | |
172 | - const: rx_lane1_sync_clk | |
173 | reg: | |
174 | minItems: 1 | |
175 | maxItems: 1 | |
7839d566 LW |
176 | reg-names: |
177 | maxItems: 1 | |
462c5c0a KK |
178 | |
179 | - if: | |
180 | properties: | |
181 | compatible: | |
182 | contains: | |
183 | enum: | |
184 | - qcom,sdm845-ufshc | |
3d8fa7a2 | 185 | - qcom,sm6350-ufshc |
462c5c0a KK |
186 | - qcom,sm8150-ufshc |
187 | then: | |
188 | properties: | |
189 | clocks: | |
190 | minItems: 9 | |
191 | maxItems: 9 | |
192 | clock-names: | |
193 | items: | |
194 | - const: core_clk | |
195 | - const: bus_aggr_clk | |
196 | - const: iface_clk | |
197 | - const: core_clk_unipro | |
198 | - const: ref_clk | |
199 | - const: tx_lane0_sync_clk | |
200 | - const: rx_lane0_sync_clk | |
201 | - const: rx_lane1_sync_clk | |
202 | - const: ice_core_clk | |
203 | reg: | |
204 | minItems: 2 | |
205 | maxItems: 2 | |
7839d566 LW |
206 | reg-names: |
207 | minItems: 2 | |
208 | required: | |
209 | - reg-names | |
462c5c0a KK |
210 | |
211 | - if: | |
212 | properties: | |
213 | compatible: | |
214 | contains: | |
215 | enum: | |
216 | - qcom,msm8996-ufshc | |
217 | then: | |
218 | properties: | |
219 | clocks: | |
220 | minItems: 11 | |
221 | maxItems: 11 | |
222 | clock-names: | |
223 | items: | |
224 | - const: core_clk_src | |
225 | - const: core_clk | |
226 | - const: bus_clk | |
227 | - const: bus_aggr_clk | |
228 | - const: iface_clk | |
229 | - const: core_clk_unipro_src | |
230 | - const: core_clk_unipro | |
231 | - const: core_clk_ice | |
232 | - const: ref_clk | |
233 | - const: tx_lane0_sync_clk | |
234 | - const: rx_lane0_sync_clk | |
235 | reg: | |
236 | minItems: 1 | |
237 | maxItems: 1 | |
7839d566 LW |
238 | reg-names: |
239 | maxItems: 1 | |
462c5c0a | 240 | |
a11eaed3 IC |
241 | - if: |
242 | properties: | |
243 | compatible: | |
244 | contains: | |
245 | enum: | |
246 | - qcom,sm6115-ufshc | |
b5237d0b | 247 | - qcom,sm6125-ufshc |
a11eaed3 IC |
248 | then: |
249 | properties: | |
250 | clocks: | |
251 | minItems: 8 | |
252 | maxItems: 8 | |
253 | clock-names: | |
254 | items: | |
255 | - const: core_clk | |
256 | - const: bus_aggr_clk | |
257 | - const: iface_clk | |
258 | - const: core_clk_unipro | |
259 | - const: ref_clk | |
260 | - const: tx_lane0_sync_clk | |
261 | - const: rx_lane0_sync_clk | |
262 | - const: ice_core_clk | |
263 | reg: | |
264 | minItems: 2 | |
265 | maxItems: 2 | |
266 | reg-names: | |
267 | minItems: 2 | |
268 | required: | |
269 | - reg-names | |
270 | ||
462c5c0a KK |
271 | # TODO: define clock bindings for qcom,msm8994-ufshc |
272 | ||
29a6d121 | 273 | - if: |
9b7c13b8 AV |
274 | required: |
275 | - qcom,ice | |
29a6d121 AV |
276 | then: |
277 | properties: | |
278 | reg: | |
279 | maxItems: 1 | |
280 | clocks: | |
7fb5aafc | 281 | minItems: 7 |
29a6d121 AV |
282 | maxItems: 8 |
283 | else: | |
284 | properties: | |
285 | reg: | |
9b7c13b8 | 286 | minItems: 1 |
29a6d121 AV |
287 | maxItems: 2 |
288 | clocks: | |
7fb5aafc | 289 | minItems: 7 |
29a6d121 AV |
290 | maxItems: 11 |
291 | ||
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292 | unevaluatedProperties: false |
293 | ||
294 | examples: | |
295 | - | | |
296 | #include <dt-bindings/clock/qcom,gcc-sm8450.h> | |
297 | #include <dt-bindings/clock/qcom,rpmh.h> | |
298 | #include <dt-bindings/gpio/gpio.h> | |
299 | #include <dt-bindings/interconnect/qcom,sm8450.h> | |
300 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
301 | ||
302 | soc { | |
303 | #address-cells = <2>; | |
304 | #size-cells = <2>; | |
305 | ||
306 | ufs@1d84000 { | |
307 | compatible = "qcom,sm8450-ufshc", "qcom,ufshc", | |
308 | "jedec,ufs-2.0"; | |
309 | reg = <0 0x01d84000 0 0x3000>; | |
310 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; | |
311 | phys = <&ufs_mem_phy_lanes>; | |
312 | phy-names = "ufsphy"; | |
313 | lanes-per-direction = <2>; | |
314 | #reset-cells = <1>; | |
315 | resets = <&gcc GCC_UFS_PHY_BCR>; | |
316 | reset-names = "rst"; | |
317 | reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; | |
318 | ||
319 | vcc-supply = <&vreg_l7b_2p5>; | |
320 | vcc-max-microamp = <1100000>; | |
321 | vccq-supply = <&vreg_l9b_1p2>; | |
322 | vccq-max-microamp = <1200000>; | |
323 | ||
324 | power-domains = <&gcc UFS_PHY_GDSC>; | |
325 | iommus = <&apps_smmu 0xe0 0x0>; | |
326 | interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, | |
327 | <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; | |
328 | interconnect-names = "ufs-ddr", "cpu-ufs"; | |
329 | ||
330 | clock-names = "core_clk", | |
331 | "bus_aggr_clk", | |
332 | "iface_clk", | |
333 | "core_clk_unipro", | |
334 | "ref_clk", | |
335 | "tx_lane0_sync_clk", | |
336 | "rx_lane0_sync_clk", | |
337 | "rx_lane1_sync_clk"; | |
338 | clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, | |
339 | <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, | |
340 | <&gcc GCC_UFS_PHY_AHB_CLK>, | |
341 | <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, | |
342 | <&rpmhcc RPMH_CXO_CLK>, | |
343 | <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, | |
344 | <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, | |
345 | <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; | |
346 | freq-table-hz = <75000000 300000000>, | |
347 | <0 0>, | |
348 | <0 0>, | |
349 | <75000000 300000000>, | |
350 | <75000000 300000000>, | |
351 | <0 0>, | |
352 | <0 0>, | |
353 | <0 0>; | |
e95094d0 | 354 | qcom,ice = <&ice>; |
462c5c0a KK |
355 | }; |
356 | }; |