[linux-2.6-block.git] / Documentation / devicetree / bindings / timer / nvidia,tegra20-timer.txt

NVIDIA Tegra20 timer

The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
running counter. The first two channels may also trigger a watchdog reset.

Required properties:

- compatible : should be "nvidia,tegra20-timer".
- reg : Specifies base physical address and size of the registers.
- interrupts : A list of 4 interrupts; one per timer channel.
- clocks : Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.

Example:

timer {
	compatible = "nvidia,tegra20-timer";
	reg = <0x60005000 0x60>;
	interrupts = <0 0 0x04
			0 1 0x04
			0 41 0x04
			0 42 0x04>;
	clocks = <&tegra_car 132>;
};
Commit	Line	Data
2f2b7fb2 SW	1	NVIDIA Tegra20 timer
	2
	3	The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
	4	running counter. The first two channels may also trigger a watchdog reset.
	5
	6	Required properties:
	7
	8	- compatible : should be "nvidia,tegra20-timer".
	9	- reg : Specifies base physical address and size of the registers.
	10	- interrupts : A list of 4 interrupts; one per timer channel.
d8f64797 SW	11	- clocks : Must contain one entry, for the module clock.
d8f64797 SW	12	See ../clocks/clock-bindings.txt for details.
2f2b7fb2 SW	13
	14	Example:
	15
	16	timer {
	17	compatible = "nvidia,tegra20-timer";
	18	reg = <0x60005000 0x60>;
	19	interrupts = <0 0 0x04
	20	0 1 0x04
	21	0 41 0x04
	22	0 42 0x04>;
d8f64797	23	clocks = <&tegra_car 132>;
2f2b7fb2	24	};