Commit | Line | Data |
---|---|---|
98c6bf2a MB |
1 | Mediatek MT6577, MT6572 and MT6589 Timers |
2 | --------------------------------------- | |
3 | ||
4 | Required properties: | |
69a462b9 | 5 | - compatible should contain: |
02eca173 | 6 | * "mediatek,mt2701-timer" for MT2701 compatible timers |
69a462b9 | 7 | * "mediatek,mt6580-timer" for MT6580 compatible timers |
013f2a23 | 8 | * "mediatek,mt6589-timer" for MT6589 compatible timers |
0c922413 | 9 | * "mediatek,mt7623-timer" for MT7623 compatible timers |
013f2a23 YC |
10 | * "mediatek,mt8127-timer" for MT8127 compatible timers |
11 | * "mediatek,mt8135-timer" for MT8135 compatible timers | |
12 | * "mediatek,mt8173-timer" for MT8173 compatible timers | |
13 | * "mediatek,mt6577-timer" for MT6577 and all above compatible timers | |
98c6bf2a MB |
14 | - reg: Should contain location and length for timers register. |
15 | - clocks: Clocks driving the timer hardware. This list should include two | |
16 | clocks. The order is system clock and as second clock the RTC clock. | |
17 | ||
18 | Examples: | |
19 | ||
20 | timer@10008000 { | |
21 | compatible = "mediatek,mt6577-timer"; | |
22 | reg = <0x10008000 0x80>; | |
23 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; | |
24 | clocks = <&system_clk>, <&rtc_clk>; | |
25 | }; |