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1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
2 | %YAML 1.2 | |
3 | --- | |
cb95de8d RH |
4 | $id: http://devicetree.org/schemas/serial/renesas,scif.yaml# |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
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6 | |
7 | title: Renesas Serial Communication Interface with FIFO (SCIF) | |
8 | ||
9 | maintainers: | |
10 | - Geert Uytterhoeven <geert+renesas@glider.be> | |
11 | ||
384d00fa GU |
12 | properties: |
13 | compatible: | |
14 | oneOf: | |
15 | - items: | |
16 | - enum: | |
17 | - renesas,scif-r7s72100 # RZ/A1H | |
18 | - const: renesas,scif # generic SCIF compatible UART | |
19 | ||
20 | - items: | |
21 | - enum: | |
22 | - renesas,scif-r7s9210 # RZ/A2 | |
23 | ||
24 | - items: | |
25 | - enum: | |
26 | - renesas,scif-r8a7778 # R-Car M1 | |
27 | - renesas,scif-r8a7779 # R-Car H1 | |
28 | - const: renesas,rcar-gen1-scif # R-Car Gen1 | |
29 | - const: renesas,scif # generic SCIF compatible UART | |
30 | ||
31 | - items: | |
32 | - enum: | |
8908a822 | 33 | - renesas,scif-r8a7742 # RZ/G1H |
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34 | - renesas,scif-r8a7743 # RZ/G1M |
35 | - renesas,scif-r8a7744 # RZ/G1N | |
36 | - renesas,scif-r8a7745 # RZ/G1E | |
37 | - renesas,scif-r8a77470 # RZ/G1C | |
38 | - renesas,scif-r8a7790 # R-Car H2 | |
39 | - renesas,scif-r8a7791 # R-Car M2-W | |
40 | - renesas,scif-r8a7792 # R-Car V2H | |
41 | - renesas,scif-r8a7793 # R-Car M2-N | |
42 | - renesas,scif-r8a7794 # R-Car E2 | |
43 | - const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G1 | |
44 | - const: renesas,scif # generic SCIF compatible UART | |
45 | ||
46 | - items: | |
47 | - enum: | |
48 | - renesas,scif-r8a774a1 # RZ/G2M | |
2108aa2a | 49 | - renesas,scif-r8a774a3 # RZ/G2M v3.0 |
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50 | - renesas,scif-r8a774b1 # RZ/G2N |
51 | - renesas,scif-r8a774c0 # RZ/G2E | |
c8d55a22 | 52 | - renesas,scif-r8a774e1 # RZ/G2H |
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53 | - renesas,scif-r8a7795 # R-Car H3 |
54 | - renesas,scif-r8a7796 # R-Car M3-W | |
55 | - renesas,scif-r8a77961 # R-Car M3-W+ | |
56 | - renesas,scif-r8a77965 # R-Car M3-N | |
57 | - renesas,scif-r8a77970 # R-Car V3M | |
58 | - renesas,scif-r8a77980 # R-Car V3H | |
59 | - renesas,scif-r8a77990 # R-Car E3 | |
60 | - renesas,scif-r8a77995 # R-Car D3 | |
61 | - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2 | |
62 | - const: renesas,scif # generic SCIF compatible UART | |
63 | ||
6aa7cee6 YS |
64 | - items: |
65 | - enum: | |
f26c65da | 66 | - renesas,scif-r8a779a0 # R-Car V3U |
6aa7cee6 | 67 | - renesas,scif-r8a779f0 # R-Car S4-8 |
fa31528a | 68 | - renesas,scif-r8a779g0 # R-Car V4H |
b464199e | 69 | - renesas,scif-r8a779h0 # R-Car V4M |
6aa7cee6 YS |
70 | - const: renesas,rcar-gen4-scif # R-Car Gen4 |
71 | - const: renesas,scif # generic SCIF compatible UART | |
72 | ||
92e06e12 LP |
73 | - items: |
74 | - enum: | |
75 | - renesas,scif-r9a07g044 # RZ/G2{L,LC} | |
b0c86a60 BD |
76 | |
77 | - items: | |
78 | - enum: | |
5698782f | 79 | - renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five |
b0c86a60 | 80 | - renesas,scif-r9a07g054 # RZ/V2L |
8e3c8252 | 81 | - renesas,scif-r9a08g045 # RZ/G3S |
ed265bc9 | 82 | - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback |
92e06e12 | 83 | |
964a80cf LP |
84 | - const: renesas,scif-r9a09g057 # RZ/V2H(P) |
85 | ||
384d00fa GU |
86 | reg: |
87 | maxItems: 1 | |
88 | ||
89 | interrupts: | |
90 | oneOf: | |
91 | - items: | |
92 | - description: A combined interrupt | |
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93 | - items: |
94 | - description: Error interrupt | |
95 | - description: Receive buffer full interrupt | |
96 | - description: Transmit buffer empty interrupt | |
97 | - description: Break interrupt | |
98 | - description: Data Ready interrupt | |
99 | - description: Transmit End interrupt | |
964a80cf LP |
100 | - description: Transmit End/Data Ready interrupt |
101 | - description: Receive buffer full interrupt (EDGE trigger) | |
102 | - description: Transmit buffer empty interrupt (EDGE trigger) | |
d057a1e3 | 103 | minItems: 4 |
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104 | |
105 | interrupt-names: | |
d057a1e3 LP |
106 | minItems: 4 |
107 | items: | |
108 | - const: eri | |
109 | - const: rxi | |
110 | - const: txi | |
111 | - const: bri | |
112 | - const: dri | |
113 | - const: tei | |
964a80cf LP |
114 | - const: tei-dri |
115 | - const: rxi-edge | |
116 | - const: txi-edge | |
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117 | |
118 | clocks: | |
119 | minItems: 1 | |
120 | maxItems: 4 | |
121 | ||
122 | clock-names: | |
123 | minItems: 1 | |
124 | maxItems: 4 | |
125 | items: | |
126 | enum: | |
127 | - fck # UART functional clock | |
128 | - sck # optional external clock input | |
129 | - brg_int # optional internal clock source for BRG frequency divider | |
130 | - scif_clk # optional external clock source for BRG frequency divider | |
131 | ||
132 | power-domains: | |
133 | maxItems: 1 | |
134 | ||
135 | resets: | |
136 | maxItems: 1 | |
137 | ||
138 | dmas: | |
0499220d RH |
139 | minItems: 2 |
140 | maxItems: 4 | |
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141 | description: |
142 | Must contain a list of pairs of references to DMA specifiers, one for | |
143 | transmission, and one for reception. | |
144 | ||
145 | dma-names: | |
146 | minItems: 2 | |
147 | maxItems: 4 | |
148 | items: | |
149 | enum: | |
150 | - tx | |
151 | - rx | |
152 | ||
153 | required: | |
154 | - compatible | |
155 | - reg | |
156 | - interrupts | |
157 | - clocks | |
158 | - clock-names | |
159 | - power-domains | |
160 | ||
220fb8ff LP |
161 | allOf: |
162 | - $ref: serial.yaml# | |
163 | ||
164 | - if: | |
165 | properties: | |
166 | compatible: | |
167 | contains: | |
168 | enum: | |
169 | - renesas,rcar-gen2-scif | |
170 | - renesas,rcar-gen3-scif | |
171 | - renesas,rcar-gen4-scif | |
172 | - renesas,scif-r9a07g044 | |
964a80cf | 173 | - renesas,scif-r9a09g057 |
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174 | then: |
175 | required: | |
176 | - resets | |
384d00fa | 177 | |
d057a1e3 LP |
178 | - if: |
179 | properties: | |
180 | compatible: | |
181 | contains: | |
182 | enum: | |
183 | - renesas,rcar-gen1-scif | |
184 | - renesas,rcar-gen2-scif | |
185 | - renesas,rcar-gen3-scif | |
186 | - renesas,rcar-gen4-scif | |
187 | then: | |
188 | properties: | |
189 | interrupts: | |
190 | maxItems: 1 | |
191 | ||
192 | interrupt-names: false | |
034e4422 LP |
193 | else: |
194 | required: | |
195 | - interrupt-names | |
d057a1e3 LP |
196 | |
197 | - if: | |
198 | properties: | |
199 | compatible: | |
200 | contains: | |
201 | enum: | |
202 | - renesas,scif-r7s72100 | |
203 | then: | |
204 | properties: | |
205 | interrupts: | |
206 | minItems: 4 | |
207 | maxItems: 4 | |
208 | ||
209 | interrupt-names: | |
210 | maxItems: 4 | |
211 | ||
212 | - if: | |
213 | properties: | |
214 | compatible: | |
215 | contains: | |
216 | enum: | |
217 | - renesas,scif-r7s9210 | |
218 | - renesas,scif-r9a07g044 | |
219 | then: | |
220 | properties: | |
221 | interrupts: | |
222 | minItems: 6 | |
964a80cf | 223 | maxItems: 6 |
d057a1e3 LP |
224 | |
225 | interrupt-names: | |
226 | minItems: 6 | |
964a80cf LP |
227 | maxItems: 6 |
228 | ||
229 | - if: | |
230 | properties: | |
231 | compatible: | |
232 | contains: | |
233 | const: renesas,scif-r9a09g057 | |
234 | then: | |
235 | properties: | |
236 | clocks: | |
237 | maxItems: 1 | |
238 | ||
239 | clock-names: | |
240 | maxItems: 1 | |
241 | ||
242 | interrupts: | |
243 | minItems: 9 | |
244 | ||
245 | interrupt-names: | |
246 | minItems: 9 | |
d057a1e3 | 247 | |
6fdc6e23 RH |
248 | unevaluatedProperties: false |
249 | ||
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250 | examples: |
251 | - | | |
252 | #include <dt-bindings/clock/r8a7791-cpg-mssr.h> | |
253 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
254 | #include <dt-bindings/power/r8a7791-sysc.h> | |
255 | aliases { | |
2115a84d | 256 | serial0 = &scif0; |
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257 | }; |
258 | ||
259 | scif0: serial@e6e60000 { | |
2115a84d KK |
260 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
261 | "renesas,scif"; | |
262 | reg = <0xe6e60000 64>; | |
263 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
264 | clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, | |
265 | <&scif_clk>; | |
266 | clock-names = "fck", "brg_int", "scif_clk"; | |
267 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; | |
268 | dma-names = "tx", "rx", "tx", "rx"; | |
269 | power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; | |
270 | resets = <&cpg 721>; | |
384d00fa | 271 | }; |