projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 6e01365c SB |
1 | * MSM Serial UARTDM |
| 2 | ||
| 3 | The MSM serial UARTDM hardware is designed for high-speed use cases where the | |
| 4 | transmit and/or receive channels can be offloaded to a dma-engine. From a | |
| 5 | software perspective it's mostly compatible with the MSM serial UART except | |
| 6 | that it supports reading and writing multiple characters at a time. | |
| 7 | ||
| 8 | Required properties: | |
| 9 | - compatible: Should contain at least "qcom,msm-uartdm". | |
| 10 | A more specific property should be specified as follows depending | |
| 11 | on the version: | |
| 12 | "qcom,msm-uartdm-v1.1" | |
| 13 | "qcom,msm-uartdm-v1.2" | |
| 14 | "qcom,msm-uartdm-v1.3" | |
| 15 | "qcom,msm-uartdm-v1.4" | |
| 16 | - reg: Should contain UART register locations and lengths. The first | |
| 17 | register shall specify the main control registers. An optional second | |
| 18 | register location shall specify the GSBI control region. | |
| 19 | "qcom,msm-uartdm-v1.3" is the only compatible value that might | |
| 20 | need the GSBI control region. | |
| 21 | - interrupts: Should contain UART interrupt. | |
| 22 | - clocks: Should contain the core clock and the AHB clock. | |
| 23 | - clock-names: Should be "core" for the core clock and "iface" for the | |
| 24 | AHB clock. | |
| 25 | ||
| 26 | Optional properties: | |
| 27 | - dmas: Should contain dma specifiers for transmit and receive channels | |
| 28 | - dma-names: Should contain "tx" for transmit and "rx" for receive channels | |
| 3a878c43 II |
29 | - qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be |
| 30 | used with TX DMA channel. Required when using DMA for transmission | |
| 7587eb18 | 31 | with UARTDM v1.3 and below. |
| 99693945 II |
32 | - qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be |
| 33 | used with RX DMA channel. Required when using DMA for reception | |
| 7587eb18 | 34 | with UARTDM v1.3 and below. |
| 6e01365c | 35 | |
| bbac3297 FR |
36 | Note: Aliases may be defined to ensure the correct ordering of the UARTs. |
| 37 | The alias serialN will result in the UART being assigned port N. If any | |
| 38 | serialN alias exists, then an alias must exist for each enabled UART. The | |
| 39 | serialN aliases should be in a .dts file instead of in a .dtsi file. | |
| 40 | ||
| 6e01365c SB |
41 | Examples: |
| 42 | ||
| bbac3297 FR |
43 | - A uartdm v1.4 device with dma capabilities. |
| 44 | ||
| 45 | serial@f991e000 { | |
| 46 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| 47 | reg = <0xf991e000 0x1000>; | |
| 48 | interrupts = <0 108 0x0>; | |
| 49 | clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>; | |
| 50 | clock-names = "core", "iface"; | |
| 51 | dmas = <&dma0 0>, <&dma0 1>; | |
| 52 | dma-names = "tx", "rx"; | |
| 53 | }; | |
| 54 | ||
| 55 | - A uartdm v1.3 device without dma capabilities and part of a GSBI complex. | |
| 56 | ||
| 57 | serial@19c40000 { | |
| 58 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
| 59 | reg = <0x19c40000 0x1000>, | |
| 60 | <0x19c00000 0x1000>; | |
| 61 | interrupts = <0 195 0x0>; | |
| 62 | clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>; | |
| 63 | clock-names = "core", "iface"; | |
| 64 | }; | |
| 65 | ||
| 66 | - serialN alias. | |
| 67 | ||
| 68 | aliases { | |
| 69 | serial0 = &uarta; | |
| 70 | serial1 = &uartc; | |
| 71 | serial2 = &uartb; | |
| 72 | }; | |
| 73 | ||
| 74 | uarta: serial@12490000 { | |
| bbac3297 FR |
75 | }; |
| 76 | ||
| 77 | uartb: serial@16340000 { | |
| bbac3297 FR |
78 | }; |
| 79 | ||
| 80 | uartc: serial@1a240000 { | |
| bbac3297 | 81 | }; |