projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| c4fcbf11 | 1 | * MediaTek Universal Asynchronous Receiver/Transmitter (UART) |
| 76ce6770 MB |
2 | |
| 3 | Required properties: | |
| 4 | - compatible should contain: | |
| 02eca173 | 5 | * "mediatek,mt2701-uart" for MT2701 compatible UARTS |
| c6f0f58a | 6 | * "mediatek,mt2712-uart" for MT2712 compatible UARTS |
| 02eca173 EL |
7 | * "mediatek,mt6580-uart" for MT6580 compatible UARTS |
| 8 | * "mediatek,mt6582-uart" for MT6582 compatible UARTS | |
| 9 | * "mediatek,mt6589-uart" for MT6589 compatible UARTS | |
| 94613fa6 | 10 | * "mediatek,mt6755-uart" for MT6755 compatible UARTS |
| eb3c74c2 | 11 | * "mediatek,mt6765-uart" for MT6765 compatible UARTS |
| 563d4f0f | 12 | * "mediatek,mt6779-uart" for MT6779 compatible UARTS |
| 02eca173 | 13 | * "mediatek,mt6795-uart" for MT6795 compatible UARTS |
| 1be88348 | 14 | * "mediatek,mt6797-uart" for MT6797 compatible UARTS |
| 5f004746 | 15 | * "mediatek,mt7622-uart" for MT7622 compatible UARTS |
| 0c922413 | 16 | * "mediatek,mt7623-uart" for MT7623 compatible UARTS |
| c4fcbf11 | 17 | * "mediatek,mt7629-uart" for MT7629 compatible UARTS |
| 481975b2 | 18 | * "mediatek,mt7986-uart", "mediatek,mt6577-uart" for MT7986 compatible UARTS |
| ab407df7 | 19 | * "mediatek,mt8127-uart" for MT8127 compatible UARTS |
| 02eca173 | 20 | * "mediatek,mt8135-uart" for MT8135 compatible UARTS |
| 83af225c | 21 | * "mediatek,mt8173-uart" for MT8173 compatible UARTS |
| 898a737c | 22 | * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS |
| 1d22c270 | 23 | * "mediatek,mt8186-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS |
| a7de3bcb | 24 | * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS |
| 214df75d | 25 | * "mediatek,mt8195-uart", "mediatek,mt6577-uart" for MT8195 compatible UARTS |
| 61a64014 | 26 | * "mediatek,mt8516-uart" for MT8516 compatible UARTS |
| 02eca173 | 27 | * "mediatek,mt6577-uart" for MT6577 and all of the above |
| 76ce6770 MB |
28 | |
| 29 | - reg: The base address of the UART register bank. | |
| 30 | ||
| 1cadfc58 CC |
31 | - interrupts: |
| 32 | index 0: an interrupt specifier for the UART controller itself | |
| 33 | index 1: optional, an interrupt specifier with edge sensitivity on Rx pin to | |
| 34 | support Rx in-band wake up. If one would like to use this feature, | |
| 35 | one must create an addtional pinctrl to reconfigure Rx pin to normal | |
| 36 | GPIO before suspend. | |
| 76ce6770 | 37 | |
| c1c325d7 SH |
38 | - clocks : Must contain an entry for each entry in clock-names. |
| 39 | See ../clocks/clock-bindings.txt for details. | |
| 40 | - clock-names: | |
| 41 | - "baud": The clock the baudrate is derived from | |
| 42 | - "bus": The bus clock for register accesses (optional) | |
| 43 | ||
| 44 | For compatibility with older device trees an unnamed clock is used for the | |
| 45 | baud clock if the baudclk does not exist. Do not use this for new designs. | |
| 76ce6770 MB |
46 | |
| 47 | Example: | |
| 48 | ||
| 49 | uart0: serial@11006000 { | |
| 50 | compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart"; | |
| 51 | reg = <0x11006000 0x400>; | |
| 1cadfc58 CC |
52 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, |
| 53 | <GIC_SPI 52 IRQ_TYPE_EDGE_FALLING>; | |
| c1c325d7 SH |
54 | clocks = <&uart_clk>, <&bus_clk>; |
| 55 | clock-names = "baud", "bus"; | |
| 1cadfc58 CC |
56 | pinctrl-names = "default", "sleep"; |
| 57 | pinctrl-0 = <&uart_pin>; | |
| 58 | pinctrl-1 = <&uart_pin_sleep>; | |
| 76ce6770 | 59 | }; |