Commit | Line | Data |
---|---|---|
61ab1a90 JI |
1 | * UART (Universal Asynchronous Receiver/Transmitter) |
2 | ||
3 | Required properties: | |
4 | - compatible : one of: | |
5 | - "ns8250" | |
6 | - "ns16450" | |
7 | - "ns16550a" | |
8 | - "ns16550" | |
9 | - "ns16750" | |
10 | - "ns16850" | |
193c9d23 PW |
11 | - For Tegra20, must contain "nvidia,tegra20-uart" |
12 | - For other Tegra, must contain '"nvidia,<chip>-uart", | |
13 | "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124, | |
14 | tegra132, or tegra210. | |
e4305f0c | 15 | - "nxp,lpc3220-uart" |
a7ae7f82 | 16 | - "ralink,rt2880-uart" |
785704d2 SW |
17 | - For MediaTek BTIF, must contain '"mediatek,<chip>-btif", |
18 | "mediatek,mtk-btif"' where <chip> is mt7622, mt7623. | |
e06c93ca LFT |
19 | - "altr,16550-FIFO32" |
20 | - "altr,16550-FIFO64" | |
21 | - "altr,16550-FIFO128" | |
7d480ef7 | 22 | - "fsl,16550-FIFO64" |
ce4ee580 | 23 | - "fsl,ns16550" |
3a50365d | 24 | - "intel,xscale-uart" |
b2ae93e0 | 25 | - "ti,da830-uart" |
7fbcf3af JK |
26 | - "aspeed,ast2400-vuart" |
27 | - "aspeed,ast2500-vuart" | |
f597fbce | 28 | - "nuvoton,npcm750-uart" |
61ab1a90 JI |
29 | - "serial" if the port type is unknown. |
30 | - reg : offset and length of the register set for the device. | |
31 | - interrupts : should contain uart interrupt. | |
ab72fa55 MK |
32 | - clock-frequency : the input clock frequency for the UART |
33 | or | |
34 | clocks phandle to refer to the clk used as per Documentation/devicetree | |
35 | /bindings/clock/clock-bindings.txt | |
61ab1a90 JI |
36 | |
37 | Optional properties: | |
38 | - current-speed : the current active speed of the UART. | |
39 | - reg-offset : offset to apply to the mapbase from the start of the registers. | |
40 | - reg-shift : quantity to shift the register offsets by. | |
7423734e JI |
41 | - reg-io-width : the size (in bytes) of the IO accesses that should be |
42 | performed on the device. There are some systems that require 32-bit | |
43 | accesses to the UART (e.g. TI davinci). | |
61ab1a90 JI |
44 | - used-by-rtas : set to indicate that the port is in use by the OpenFirmware |
45 | RTAS and should not be registered. | |
fde8be29 GJ |
46 | - no-loopback-test: set to indicate that the port does not implements loopback |
47 | test mode | |
9f1ca068 | 48 | - fifo-size: the fifo size of the UART. |
b0b8c84c HK |
49 | - auto-flow-control: one way to enable automatic flow control support. The |
50 | driver is allowed to detect support for the capability even without this | |
51 | property. | |
51311eaa TT |
52 | - tx-threshold: Specify the TX FIFO low water indication for parts with |
53 | programmable TX FIFO thresholds. | |
e2860e1f | 54 | - resets : phandle + reset specifier pairs |
bdb48e4c | 55 | - overrun-throttle-ms : how long to pause uart rx when input overrun is encountered. |
4a96895f YY |
56 | - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD |
57 | line respectively. It will use specified GPIO instead of the peripheral | |
58 | function pin for the UART feature. If unsure, don't specify this property. | |
61ab1a90 | 59 | |
ce4ee580 BS |
60 | Note: |
61 | * fsl,ns16550: | |
62 | ------------ | |
63 | Freescale DUART is very similar to the PC16552D (and to a | |
64 | pair of NS16550A), albeit with some nonstandard behavior such as | |
65 | erratum A-004737 (relating to incorrect BRK handling). | |
66 | ||
67 | Represents a single port that is compatible with the DUART found | |
68 | on many Freescale chips (examples include mpc8349, mpc8548, | |
69 | mpc8641d, p4080 and ls2085a). | |
70 | ||
61ab1a90 JI |
71 | Example: |
72 | ||
73 | uart@80230000 { | |
74 | compatible = "ns8250"; | |
75 | reg = <0x80230000 0x100>; | |
76 | clock-frequency = <3686400>; | |
77 | interrupts = <10>; | |
78 | reg-shift = <2>; | |
79 | }; | |
4a96895f YY |
80 | |
81 | Example for OMAP UART using GPIO-based modem control signals: | |
82 | ||
83 | uart4: serial@49042000 { | |
84 | compatible = "ti,omap3-uart"; | |
85 | reg = <0x49042000 0x400>; | |
86 | interrupts = <80>; | |
87 | ti,hwmods = "uart4"; | |
88 | clock-frequency = <48000000>; | |
89 | cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; | |
90 | rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; | |
91 | dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; | |
92 | dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; | |
93 | dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; | |
94 | rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; | |
95 | }; |