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1 | # SPDX-License-Identifier: (GPL-2.0 OR MIT) |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/riscv/cpus.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
3367934d | 7 | title: RISC-V CPUs |
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8 | |
9 | maintainers: | |
10 | - Paul Walmsley <paul.walmsley@sifive.com> | |
11 | - Palmer Dabbelt <palmer@sifive.com> | |
299824e6 | 12 | - Conor Dooley <conor@kernel.org> |
4fd669a8 | 13 | |
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14 | description: | |
15 | This document uses some terminology common to the RISC-V community | |
16 | that is not widely used, the definitions of which are listed here: | |
17 | ||
18 | hart: A hardware execution context, which contains all the state | |
19 | mandated by the RISC-V ISA: a PC and some registers. This | |
20 | terminology is designed to disambiguate software's view of execution | |
21 | contexts from any particular microarchitectural implementation | |
22 | strategy. For example, an Intel laptop containing one socket with | |
23 | two cores, each of which has two hyperthreads, could be described as | |
24 | having four harts. | |
25 | ||
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26 | allOf: |
27 | - $ref: /schemas/cpu.yaml# | |
aeb71e42 | 28 | - $ref: extensions.yaml |
3c1b4758 | 29 | |
4fd669a8 | 30 | properties: |
7d9ef7f3 | 31 | compatible: |
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32 | oneOf: |
33 | - items: | |
34 | - enum: | |
4a6b93f5 | 35 | - amd,mbv32 |
9f643dc2 | 36 | - andestech,ax45mp |
57e1b873 | 37 | - canaan,k210 |
75e6d724 | 38 | - sifive,bullet0 |
9af865d9 | 39 | - sifive,e5 |
75e6d724 | 40 | - sifive,e7 |
75e6d724 | 41 | - sifive,e71 |
57e1b873 | 42 | - sifive,rocket0 |
8868caa2 | 43 | - sifive,s7 |
9af865d9 | 44 | - sifive,u5 |
57e1b873 | 45 | - sifive,u54 |
75e6d724 | 46 | - sifive,u7 |
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47 | - sifive,u74 |
48 | - sifive,u74-mc | |
41adc2fb SH |
49 | - thead,c906 |
50 | - thead,c910 | |
b965d9a9 | 51 | - thead,c920 |
9af865d9 | 52 | - const: riscv |
f46428f0 KK |
53 | - items: |
54 | - enum: | |
55 | - sifive,e51 | |
56 | - sifive,u54-mc | |
57 | - const: sifive,rocket0 | |
58 | - const: riscv | |
9af865d9 | 59 | - const: riscv # Simulator only |
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60 | description: |
61 | Identifies that the hart uses the RISC-V instruction set | |
62 | and identifies the type of the hart. | |
63 | ||
64 | mmu-type: | |
7d9ef7f3 | 65 | description: |
a4528161 SH |
66 | Identifies the largest MMU address translation mode supported by |
67 | this hart. These values originate from the RISC-V Privileged | |
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68 | Specification document, available from |
69 | https://riscv.org/specifications/ | |
f2023385 | 70 | $ref: /schemas/types.yaml#/definitions/string |
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71 | enum: |
72 | - riscv,sv32 | |
73 | - riscv,sv39 | |
74 | - riscv,sv48 | |
d4dda690 | 75 | - riscv,sv57 |
7ef71c71 | 76 | - riscv,none |
7d9ef7f3 | 77 | |
d1afce67 HS |
78 | riscv,cbom-block-size: |
79 | $ref: /schemas/types.yaml#/definitions/uint32 | |
80 | description: | |
81 | The blocksize in bytes for the Zicbom cache operations. | |
82 | ||
ea20f117 AJ |
83 | riscv,cboz-block-size: |
84 | $ref: /schemas/types.yaml#/definitions/uint32 | |
85 | description: | |
86 | The blocksize in bytes for the Zicboz cache operations. | |
87 | ||
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88 | # RISC-V has multiple properties for cache op block sizes as the sizes |
89 | # differ between individual CBO extensions | |
90 | cache-op-block-size: false | |
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91 | # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here |
92 | timebase-frequency: false | |
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93 | |
94 | interrupt-controller: | |
95 | type: object | |
11b1c9cd | 96 | additionalProperties: false |
7d9ef7f3 | 97 | description: Describes the CPU's local interrupt controller |
4fd669a8 | 98 | |
4fd669a8 | 99 | properties: |
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100 | '#interrupt-cells': |
101 | const: 1 | |
4fd669a8 | 102 | |
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103 | compatible: |
104 | const: riscv,cpu-intc | |
4fd669a8 | 105 | |
7d9ef7f3 | 106 | interrupt-controller: true |
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107 | |
108 | required: | |
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109 | - '#interrupt-cells' |
110 | - compatible | |
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111 | - interrupt-controller |
112 | ||
1bd524f7 | 113 | cpu-idle-states: |
f2023385 | 114 | $ref: /schemas/types.yaml#/definitions/phandle-array |
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115 | items: |
116 | maxItems: 1 | |
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117 | description: | |
118 | List of phandles to idle state nodes supported | |
119 | by this hart (see ./idle-states.yaml). | |
120 | ||
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121 | capacity-dmips-mhz: |
122 | description: | |
123 | u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in | |
124 | DMIPS/MHz, relative to highest capacity-dmips-mhz | |
125 | in the system. | |
126 | ||
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127 | anyOf: |
128 | - required: | |
129 | - riscv,isa | |
130 | - required: | |
131 | - riscv,isa-base | |
132 | ||
133 | dependencies: | |
134 | riscv,isa-base: [ "riscv,isa-extensions" ] | |
135 | riscv,isa-extensions: [ "riscv,isa-base" ] | |
136 | ||
7d9ef7f3 | 137 | required: |
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138 | - interrupt-controller |
139 | ||
1ffe6ddc | 140 | unevaluatedProperties: false |
6a0e321e | 141 | |
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142 | examples: |
143 | - | | |
144 | // Example 1: SiFive Freedom U540G Development Kit | |
145 | cpus { | |
146 | #address-cells = <1>; | |
147 | #size-cells = <0>; | |
148 | timebase-frequency = <1000000>; | |
149 | cpu@0 { | |
150 | clock-frequency = <0>; | |
151 | compatible = "sifive,rocket0", "riscv"; | |
152 | device_type = "cpu"; | |
153 | i-cache-block-size = <64>; | |
154 | i-cache-sets = <128>; | |
155 | i-cache-size = <16384>; | |
156 | reg = <0>; | |
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157 | riscv,isa-base = "rv64i"; |
158 | riscv,isa-extensions = "i", "m", "a", "c"; | |
159 | ||
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160 | cpu_intc0: interrupt-controller { |
161 | #interrupt-cells = <1>; | |
162 | compatible = "riscv,cpu-intc"; | |
163 | interrupt-controller; | |
164 | }; | |
165 | }; | |
166 | cpu@1 { | |
167 | clock-frequency = <0>; | |
168 | compatible = "sifive,rocket0", "riscv"; | |
169 | d-cache-block-size = <64>; | |
170 | d-cache-sets = <64>; | |
171 | d-cache-size = <32768>; | |
172 | d-tlb-sets = <1>; | |
173 | d-tlb-size = <32>; | |
174 | device_type = "cpu"; | |
175 | i-cache-block-size = <64>; | |
176 | i-cache-sets = <64>; | |
177 | i-cache-size = <32768>; | |
178 | i-tlb-sets = <1>; | |
179 | i-tlb-size = <32>; | |
180 | mmu-type = "riscv,sv39"; | |
181 | reg = <1>; | |
4fd669a8 | 182 | tlb-split; |
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183 | riscv,isa-base = "rv64i"; |
184 | riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; | |
185 | ||
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186 | cpu_intc1: interrupt-controller { |
187 | #interrupt-cells = <1>; | |
188 | compatible = "riscv,cpu-intc"; | |
189 | interrupt-controller; | |
190 | }; | |
191 | }; | |
192 | }; | |
193 | ||
194 | - | | |
195 | // Example 2: Spike ISA Simulator with 1 Hart | |
196 | cpus { | |
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197 | #address-cells = <1>; |
198 | #size-cells = <0>; | |
199 | cpu@0 { | |
200 | device_type = "cpu"; | |
201 | reg = <0>; | |
202 | compatible = "riscv"; | |
3cdb0157 | 203 | mmu-type = "riscv,sv48"; |
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204 | riscv,isa-base = "rv64i"; |
205 | riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; | |
206 | ||
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207 | interrupt-controller { |
208 | #interrupt-cells = <1>; | |
209 | interrupt-controller; | |
210 | compatible = "riscv,cpu-intc"; | |
211 | }; | |
212 | }; | |
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213 | }; |
214 | ... |