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e7eda91f BS |
1 | CSR SiRFSoC Reset Controller |
2 | ====================================== | |
3 | ||
4 | Please also refer to reset.txt in this directory for common reset | |
5 | controller binding usage. | |
6 | ||
7 | Required properties: | |
8 | - compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc" | |
9 | - reg: should be register base and length as documented in the | |
10 | datasheet | |
11 | - #reset-cells: 1, see below | |
12 | ||
13 | example: | |
14 | ||
15 | rstc: reset-controller@88010000 { | |
16 | compatible = "sirf,prima2-rstc"; | |
17 | reg = <0x88010000 0x1000>; | |
18 | #reset-cells = <1>; | |
19 | }; | |
20 | ||
21 | Specifying reset lines connected to IP modules | |
22 | ============================================== | |
23 | ||
24 | The reset controller(rstc) manages various reset sources. This module provides | |
25 | reset signals for most blocks in system. Those device nodes should specify the | |
26 | reset line on the rstc in their resets property, containing a phandle to the | |
27 | rstc device node and a RESET_INDEX specifying which module to reset, as described | |
28 | in reset.txt. | |
29 | ||
30 | For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers. | |
31 | For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose | |
32 | rest_bit is in SW_RST1, its RESET_INDEX is 32~63. | |
33 | ||
34 | example: | |
35 | ||
36 | vpp@90020000 { | |
37 | compatible = "sirf,prima2-vpp"; | |
38 | reg = <0x90020000 0x10000>; | |
39 | interrupts = <31>; | |
40 | clocks = <&clks 35>; | |
41 | resets = <&rstc 6>; | |
42 | }; |