Commit | Line | Data |
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0e37f88d MR |
1 | * Allwinner A1X Pin Controller |
2 | ||
3 | The pins controlled by sunXi pin controller are organized in banks, | |
4 | each bank has 32 pins. Each pin has 7 multiplexing functions, with | |
5 | the first two functions being GPIO in and out. The configuration on | |
6 | the pins includes drive strength and pull-up. | |
7 | ||
8 | Required properties: | |
4091fb95 | 9 | - compatible: Should be one of the following (depending on your SoC): |
02b5269a BB |
10 | "allwinner,sun4i-a10-pinctrl" |
11 | "allwinner,sun5i-a10s-pinctrl" | |
12 | "allwinner,sun5i-a13-pinctrl" | |
13 | "allwinner,sun6i-a31-pinctrl" | |
47cf4b32 | 14 | "allwinner,sun6i-a31s-pinctrl" |
02b5269a BB |
15 | "allwinner,sun6i-a31-r-pinctrl" |
16 | "allwinner,sun7i-a20-pinctrl" | |
4c821d1c | 17 | "allwinner,sun8i-a23-pinctrl" |
d22bf40f | 18 | "allwinner,sun8i-a23-r-pinctrl" |
7164873e | 19 | "allwinner,sun8i-a33-pinctrl" |
0eccc9cb MR |
20 | "allwinner,sun9i-a80-pinctrl" |
21 | "allwinner,sun9i-a80-r-pinctrl" | |
4730f33f | 22 | "allwinner,sun8i-a83t-pinctrl" |
a5905955 | 23 | "allwinner,sun8i-a83t-r-pinctrl" |
e87623cb | 24 | "allwinner,sun8i-h3-pinctrl" |
4919a700 | 25 | "allwinner,sun8i-h3-r-pinctrl" |
48f471c7 | 26 | "allwinner,sun8i-r40-pinctrl" |
96851d39 | 27 | "allwinner,sun50i-a64-pinctrl" |
9836b1ac | 28 | "allwinner,sun50i-a64-r-pinctrl" |
caf9db13 | 29 | "allwinner,sun50i-h5-pinctrl" |
c8a83090 | 30 | "allwinner,sun50i-h6-pinctrl" |
ac91ab51 | 31 | "nextthing,gr8-pinctrl" |
7164873e | 32 | |
0e37f88d MR |
33 | - reg: Should contain the register physical address and length for the |
34 | pin controller. | |
35 | ||
7c926492 MR |
36 | - clocks: phandle to the clocks feeding the pin controller: |
37 | - "apb": the gated APB parent clock | |
38 | - "hosc": the high frequency oscillator in the system | |
39 | - "losc": the low frequency oscillator in the system | |
40 | ||
41 | Note: For backward compatibility reasons, the hosc and losc clocks are only | |
42 | required if you need to use the optional input-debounce property. Any new | |
43 | device tree should set them. | |
44 | ||
45 | Optional properties: | |
46 | - input-debounce: Array of debouncing periods in microseconds. One period per | |
47 | irq bank found in the controller. 0 if no setup required. | |
48 | ||
49 | ||
0e37f88d MR |
50 | Please refer to pinctrl-bindings.txt in this directory for details of the |
51 | common pinctrl bindings used by client devices. | |
52 | ||
53 | A pinctrl node should contain at least one subnodes representing the | |
54 | pinctrl groups available on the machine. Each subnode will list the | |
55 | pins it needs, and how they should be configured, with regard to muxer | |
56 | configuration, drive strength and pullups. If one of these options is | |
57 | not set, its actual value will be unspecified. | |
58 | ||
b614e905 MC |
59 | Allwinner A1X Pin Controller supports the generic pin multiplexing and |
60 | configuration bindings. For details on each properties, you can refer to | |
61 | ./pinctrl-bindings.txt. | |
dfdad68f MR |
62 | |
63 | Required sub-node properties: | |
64 | - pins | |
65 | - function | |
66 | ||
67 | Optional sub-node properties: | |
68 | - bias-disable | |
69 | - bias-pull-up | |
70 | - bias-pull-down | |
71 | - drive-strength | |
72 | ||
73 | *** Deprecated pin configuration and multiplexing binding | |
74 | ||
0e37f88d MR |
75 | Required subnode-properties: |
76 | ||
77 | - allwinner,pins: List of strings containing the pin name. | |
78 | - allwinner,function: Function to mux the pins listed above to. | |
79 | ||
80 | Optional subnode-properties: | |
81 | - allwinner,drive: Integer. Represents the current sent to the pin | |
82 | 0: 10 mA | |
83 | 1: 20 mA | |
84 | 2: 30 mA | |
85 | 3: 40 mA | |
86 | - allwinner,pull: Integer. | |
87 | 0: No resistor | |
88 | 1: Pull-up resistor | |
89 | 2: Pull-down resistor | |
90 | ||
91 | Examples: | |
92 | ||
48c926cd | 93 | pio: pinctrl@1c20800 { |
0e37f88d MR |
94 | compatible = "allwinner,sun5i-a13-pinctrl"; |
95 | reg = <0x01c20800 0x400>; | |
96 | #address-cells = <1>; | |
97 | #size-cells = <0>; | |
98 | ||
99 | uart1_pins_a: uart1@0 { | |
100 | allwinner,pins = "PE10", "PE11"; | |
101 | allwinner,function = "uart1"; | |
102 | allwinner,drive = <0>; | |
103 | allwinner,pull = <0>; | |
104 | }; | |
105 | ||
106 | uart1_pins_b: uart1@1 { | |
107 | allwinner,pins = "PG3", "PG4"; | |
108 | allwinner,function = "uart1"; | |
109 | allwinner,drive = <0>; | |
110 | allwinner,pull = <0>; | |
111 | }; | |
112 | }; | |
d8323c6b MR |
113 | |
114 | ||
115 | GPIO and interrupt controller | |
116 | ----------------------------- | |
117 | ||
118 | This hardware also acts as a GPIO controller and an interrupt | |
119 | controller. | |
120 | ||
121 | Consumers that would want to refer to one or the other (or both) | |
122 | should provide through the usual *-gpios and interrupts properties a | |
123 | cell with 3 arguments, first the number of the bank, then the pin | |
124 | inside that bank, and finally the flags for the GPIO/interrupts. | |
125 | ||
126 | Example: | |
127 | ||
128 | xio: gpio@38 { | |
129 | compatible = "nxp,pcf8574a"; | |
130 | reg = <0x38>; | |
131 | ||
132 | gpio-controller; | |
133 | #gpio-cells = <2>; | |
134 | ||
135 | interrupt-parent = <&pio>; | |
136 | interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>; | |
137 | interrupt-controller; | |
138 | #interrupt-cells = <2>; | |
139 | }; | |
140 | ||
141 | reg_usb1_vbus: usb1-vbus { | |
142 | compatible = "regulator-fixed"; | |
143 | regulator-name = "usb1-vbus"; | |
144 | regulator-min-microvolt = <5000000>; | |
145 | regulator-max-microvolt = <5000000>; | |
146 | gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; | |
147 | }; |