projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 270d5aad KH |
1 | Socionext UniPhier USB3 Super-Speed (SS) PHY |
| 2 | ||
| 3 | This describes the devicetree bindings for PHY interfaces built into | |
| 4 | USB3 controller implemented on Socionext UniPhier SoCs. | |
| 5 | Although the controller includes High-Speed PHY and Super-Speed PHY, | |
| 6 | this describes about Super-Speed PHY. | |
| 7 | ||
| 8 | Required properties: | |
| 9 | - compatible: Should contain one of the following: | |
| 10 | "socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC | |
| f13200bb | 11 | "socionext,uniphier-pro5-usb3-ssphy" - for Pro5 SoC |
| 270d5aad KH |
12 | "socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC |
| 13 | "socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC | |
| 14 | "socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC | |
| 15 | - reg: Specifies offset and length of the register set for the device. | |
| 16 | - #phy-cells: Should be 0. | |
| 17 | - clocks: A list of phandles to the clock gate for USB3 glue layer. | |
| 18 | According to the clock-names, appropriate clocks are required. | |
| 19 | - clock-names: | |
| f13200bb | 20 | "gio", "link" - for Pro4 and Pro5 SoC |
| 270d5aad KH |
21 | "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional. |
| 22 | "phy", "link" - for others | |
| 23 | - resets: A list of phandles to the reset control for USB3 glue layer. | |
| 24 | According to the reset-names, appropriate resets are required. | |
| 25 | - reset-names: | |
| f13200bb | 26 | "gio", "link" - for Pro4 and Pro5 SoC |
| 270d5aad KH |
27 | "phy", "link" - for others |
| 28 | ||
| 29 | Optional properties: | |
| 30 | - vbus-supply: A phandle to the regulator for USB VBUS. | |
| 31 | ||
| 32 | Refer to phy/phy-bindings.txt for the generic PHY binding properties. | |
| 33 | ||
| 34 | Example: | |
| 35 | ||
| 36 | usb-glue@65b00000 { | |
| 37 | compatible = "socionext,uniphier-ld20-dwc3-glue", | |
| 38 | "simple-mfd"; | |
| 39 | #address-cells = <1>; | |
| 40 | #size-cells = <1>; | |
| 41 | ranges = <0 0x65b00000 0x400>; | |
| 42 | ||
| 43 | usb_vbus0: regulator { | |
| 44 | ... | |
| 45 | }; | |
| 46 | ||
| 47 | usb_ssphy0: ss-phy@300 { | |
| 48 | compatible = "socionext,uniphier-ld20-usb3-ssphy"; | |
| 49 | reg = <0x300 0x10>; | |
| 50 | #phy-cells = <0>; | |
| 51 | clock-names = "link", "phy"; | |
| 52 | clocks = <&sys_clk 14>, <&sys_clk 16>; | |
| 53 | reset-names = "link", "phy"; | |
| 54 | resets = <&sys_rst 14>, <&sys_rst 16>; | |
| 55 | vbus-supply = <&usb_vbus0>; | |
| 56 | }; | |
| 57 | ... | |
| 58 | }; |