Commit | Line | Data |
---|---|---|
8d7212bc | 1 | TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs |
657b306a | 2 | |
d95faaec RQ |
3 | OMAP CONTROL PHY |
4 | ||
5 | Required properties: | |
6 | - compatible: Should be one of | |
7 | "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4. | |
8 | "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register | |
9 | e.g. USB2_PHY on OMAP5. | |
10 | "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control | |
11 | e.g. USB3 PHY and SATA PHY on OMAP5. | |
f0e2cf7b KVA |
12 | "ti,control-phy-pcie" - for pcie to support external clock for pcie and to |
13 | set PCS delay value. | |
14 | e.g. PCIE PHY in DRA7x | |
e9995209 | 15 | "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on |
d95faaec | 16 | DRA7 platform. |
e9995209 | 17 | "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on |
d95faaec | 18 | AM437 platform. |
f0e2cf7b KVA |
19 | - reg : register ranges as listed in the reg-names property |
20 | - reg-names: "otghs_control" for control-phy-otghs | |
21 | "power", "pcie_pcs" and "control_sma" for control-phy-pcie | |
22 | "power" for all other types | |
d95faaec RQ |
23 | |
24 | omap_control_usb: omap-control-usb@4a002300 { | |
25 | compatible = "ti,control-phy-otghs"; | |
26 | reg = <0x4a00233c 0x4>; | |
27 | reg-names = "otghs_control"; | |
28 | }; | |
29 | ||
657b306a KVA |
30 | OMAP USB2 PHY |
31 | ||
32 | Required properties: | |
33 | - compatible: Should be "ti,omap-usb2" | |
a0ceee58 SN |
34 | Should be "ti,dra7x-usb2" for the 1st instance of USB2 PHY on |
35 | DRA7x | |
9955a783 KVA |
36 | Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY |
37 | in DRA7x | |
ca784be3 | 38 | - reg : Address and length of the register set for the device. |
975d963e KVA |
39 | - #phy-cells: determine the number of cells that should be given in the |
40 | phandle while referencing this phy. | |
54f4d144 RQ |
41 | - clocks: a list of phandles and clock-specifier pairs, one for each entry in |
42 | clock-names. | |
43 | - clock-names: should include: | |
44 | * "wkupclk" - wakeup clock. | |
45 | * "refclk" - reference clock (optional). | |
657b306a | 46 | |
9955a783 | 47 | Deprecated properties: |
01658f0f KVA |
48 | - ctrl-module : phandle of the control module used by PHY driver to power on |
49 | the PHY. | |
50 | ||
9955a783 KVA |
51 | Recommended properies: |
52 | - syscon-phy-power : phandle/offset pair. Phandle to the system control | |
53 | module and the register offset to power on/off the PHY. | |
54 | ||
657b306a KVA |
55 | This is usually a subnode of ocp2scp to which it is connected. |
56 | ||
57 | usb2phy@4a0ad080 { | |
58 | compatible = "ti,omap-usb2"; | |
ca784be3 | 59 | reg = <0x4a0ad080 0x58>; |
01658f0f | 60 | ctrl-module = <&omap_control_usb>; |
975d963e | 61 | #phy-cells = <0>; |
54f4d144 RQ |
62 | clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; |
63 | clock-names = "wkupclk", "refclk"; | |
657b306a | 64 | }; |
57f6ce07 | 65 | |
8d7212bc | 66 | TI PIPE3 PHY |
57f6ce07 KVA |
67 | |
68 | Required properties: | |
99bbd48c KVA |
69 | - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or |
70 | "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated. | |
57f6ce07 KVA |
71 | - reg : Address and length of the register set for the device. |
72 | - reg-names: The names of the register addresses corresponding to the registers | |
73 | filled in "reg". | |
975d963e KVA |
74 | - #phy-cells: determine the number of cells that should be given in the |
75 | phandle while referencing this phy. | |
57554008 RQ |
76 | - clocks: a list of phandles and clock-specifier pairs, one for each entry in |
77 | clock-names. | |
78 | - clock-names: should include: | |
79 | * "wkupclk" - wakeup clock. | |
80 | * "sysclk" - system clock. | |
81 | * "refclk" - reference clock. | |
99bbd48c KVA |
82 | * "dpll_ref" - external dpll ref clk |
83 | * "dpll_ref_m2" - external dpll ref clk | |
84 | * "phy-div" - divider for apll | |
85 | * "div-clk" - apll clock | |
57f6ce07 KVA |
86 | |
87 | Optional properties: | |
99bbd48c KVA |
88 | - id: If there are multiple instance of the same type, in order to |
89 | differentiate between each instance "id" can be used (e.g., multi-lane PCIe | |
90 | PHY). If "id" is not provided, it is set to default value of '1'. | |
c934b361 RQ |
91 | - syscon-pllreset: Handle to system control region that contains the |
92 | CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0 | |
93 | register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. | |
3f2362c5 KVA |
94 | - syscon-pcs : phandle/offset pair. Phandle to the system control module and the |
95 | register offset to write the PCS delay value. | |
57f6ce07 | 96 | |
c396a1c7 KVA |
97 | Deprecated properties: |
98 | - ctrl-module : phandle of the control module used by PHY driver to power on | |
99 | the PHY. | |
100 | ||
101 | Recommended properies: | |
102 | - syscon-phy-power : phandle/offset pair. Phandle to the system control | |
103 | module and the register offset to power on/off the PHY. | |
104 | ||
57f6ce07 KVA |
105 | This is usually a subnode of ocp2scp to which it is connected. |
106 | ||
107 | usb3phy@4a084400 { | |
8d7212bc | 108 | compatible = "ti,phy-usb3"; |
57f6ce07 KVA |
109 | reg = <0x4a084400 0x80>, |
110 | <0x4a084800 0x64>, | |
111 | <0x4a084c00 0x40>; | |
112 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
113 | ctrl-module = <&omap_control_usb>; | |
975d963e | 114 | #phy-cells = <0>; |
57554008 RQ |
115 | clocks = <&usb_phy_cm_clk32k>, |
116 | <&sys_clkin>, | |
117 | <&usb_otg_ss_refclk960m>; | |
118 | clock-names = "wkupclk", | |
119 | "sysclk", | |
120 | "refclk"; | |
57f6ce07 | 121 | }; |
c934b361 RQ |
122 | |
123 | sata_phy: phy@4A096000 { | |
124 | compatible = "ti,phy-pipe3-sata"; | |
125 | reg = <0x4A096000 0x80>, /* phy_rx */ | |
126 | <0x4A096400 0x64>, /* phy_tx */ | |
127 | <0x4A096800 0x40>; /* pll_ctrl */ | |
128 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
129 | ctrl-module = <&omap_control_sata>; | |
130 | clocks = <&sys_clkin1>, <&sata_ref_clk>; | |
131 | clock-names = "sysclk", "refclk"; | |
132 | syscon-pllreset = <&scm_conf 0x3fc>; | |
133 | #phy-cells = <0>; | |
134 | }; |