[linux-block.git] / Documentation / devicetree / bindings / phy / qcom-qmp-phy.txt

Qualcomm QMP PHY controller
===========================

QMP phy controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

Required properties:
 - compatible: compatible list, contains:
	       "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
	       "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
	       "qcom,msm8996-qmp-ufs-phy" for 14nm UFS phy on msm8996,
	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
	       "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
	       "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
	       "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
	       "qcom,sdm845-qhp-pcie-phy" for QHP PCIe phy on sdm845,
	       "qcom,sdm845-qmp-pcie-phy" for QMP PCIe phy on sdm845,
	       "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
	       "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
	       "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845,
	       "qcom,sm8150-qmp-ufs-phy" for UFS QMP phy on sm8150.

- reg:
  - index 0: address and length of register set for PHY's common
             serdes block.
  - index 1: address and length of the DP_COM control block (for
             "qcom,sdm845-qmp-usb3-phy" only).

- reg-names:
  - For "qcom,sdm845-qmp-usb3-phy":
    - Should be: "reg-base", "dp_com"
  - For all others:
    - The reg-names property shouldn't be defined.

 - #address-cells: must be 1
 - #size-cells: must be 1
 - ranges: must be present

 - clocks: a list of phandles and clock-specifier pairs,
	   one for each entry in clock-names.
 - clock-names: "cfg_ahb" for phy config clock,
		"aux" for phy aux clock,
		"ref" for 19.2 MHz ref clk,
		"com_aux" for phy common block aux clock,
		"ref_aux" for phy reference aux clock,

		For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
		For "qcom,msm8996-qmp-pcie-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,msm8996-qmp-ufs-phy" must contain:
			"ref".
		For "qcom,msm8996-qmp-usb3-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,msm8998-qmp-usb3-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,msm8998-qmp-ufs-phy" must contain:
			"ref", "ref_aux".
		For "qcom,msm8998-qmp-pcie-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,sdm845-qhp-pcie-phy" must contain:
			"aux", "cfg_ahb", "ref", "refgen".
		For "qcom,sdm845-qmp-pcie-phy" must contain:
			"aux", "cfg_ahb", "ref", "refgen".
		For "qcom,sdm845-qmp-usb3-phy" must contain:
			"aux", "cfg_ahb", "ref", "com_aux".
		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
			"aux", "cfg_ahb", "ref", "com_aux".
		For "qcom,sdm845-qmp-ufs-phy" must contain:
			"ref", "ref_aux".
		For "qcom,sm8150-qmp-ufs-phy" must contain:
			"ref", "ref_aux".

 - resets: a list of phandles and reset controller specifier pairs,
	   one for each entry in reset-names.
 - reset-names: "phy" for reset of phy block,
		"common" for phy common block reset,
		"cfg" for phy's ahb cfg block reset,
		"ufsphy" for the PHY reset in the UFS controller.

		For "qcom,ipq8074-qmp-pcie-phy" must contain:
			"phy", "common".
		For "qcom,msm8996-qmp-pcie-phy" must contain:
			"phy", "common", "cfg".
		For "qcom,msm8996-qmp-ufs-phy": must contain:
			"ufsphy".
		For "qcom,msm8996-qmp-usb3-phy" must contain
			"phy", "common".
		For "qcom,msm8998-qmp-usb3-phy" must contain
			"phy", "common".
		For "qcom,msm8998-qmp-ufs-phy": must contain:
			"ufsphy".
		For "qcom,msm8998-qmp-pcie-phy" must contain:
			"phy", "common".
		For "qcom,sdm845-qhp-pcie-phy" must contain:
			"phy".
		For "qcom,sdm845-qmp-pcie-phy" must contain:
			"phy".
		For "qcom,sdm845-qmp-usb3-phy" must contain:
			"phy", "common".
		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
			"phy", "common".
		For "qcom,sdm845-qmp-ufs-phy": must contain:
			"ufsphy".
		For "qcom,sm8150-qmp-ufs-phy": must contain:
			"ufsphy".

 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.

Optional properties:
 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
			pll block.

Required nodes:
 - Each device node of QMP phy is required to have as many child nodes as
   the number of lanes the PHY has.

Required properties for child nodes of PCIe PHYs (one child per lane):
 - reg: list of offset and length pairs of register sets for PHY blocks -
	tx, rx, pcs, and pcs_misc (optional).
 - #phy-cells: must be 0

Required properties for a single "lanes" child node of non-PCIe PHYs:
 - reg: list of offset and length pairs of register sets for PHY blocks
	For 1-lane devices:
		tx, rx, pcs, and (optionally) pcs_misc
	For 2-lane devices:
		tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
 - #phy-cells: must be 0

Required properties for child node of PCIe and USB3 qmp phys:
 - clocks: a list of phandles and clock-specifier pairs,
	   one for each entry in clock-names.
 - clock-names: Must contain following:
		 "pipe<lane-number>" for pipe clock specific to each lane.
 - clock-output-names: Name of the PHY clock that will be the parent for
		       the above pipe clock.
	For "qcom,ipq8074-qmp-pcie-phy":
		- "pcie20_phy0_pipe_clk"	Pipe Clock parent
			(or)
		  "pcie20_phy1_pipe_clk"
 - #clock-cells: must be 0
    - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
      gate-controlled by the gcc.

Required properties for child node of PHYs with lane reset, AKA:
	"qcom,msm8996-qmp-pcie-phy"
 - resets: a list of phandles and reset controller specifier pairs,
	   one for each entry in reset-names.
 - reset-names: Must contain following:
		 "lane<lane-number>" for reset specific to each lane.

Example:
	phy@34000 {
		compatible = "qcom,msm8996-qmp-pcie-phy";
		reg = <0x34000 0x488>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
			<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
			<&gcc GCC_PCIE_CLKREF_CLK>;
		clock-names = "aux", "cfg_ahb", "ref";

		vdda-phy-supply = <&pm8994_l28>;
		vdda-pll-supply = <&pm8994_l12>;

		resets = <&gcc GCC_PCIE_PHY_BCR>,
			<&gcc GCC_PCIE_PHY_COM_BCR>,
			<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
		reset-names = "phy", "common", "cfg";

		pciephy_0: lane@35000 {
			reg = <0x35000 0x130>,
				<0x35200 0x200>,
				<0x35400 0x1dc>;
			#clock-cells = <0>;
			#phy-cells = <0>;

			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
			clock-names = "pipe0";
			clock-output-names = "pcie_0_pipe_clk_src";
			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
			reset-names = "lane0";
		};

		pciephy_1: lane@36000 {
		...
		...
	};

	phy@88eb000 {
		compatible = "qcom,sdm845-qmp-usb3-uni-phy";
		reg = <0x88eb000 0x18c>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
			 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
			 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
			 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
		clock-names = "aux", "cfg_ahb", "ref", "com_aux";

		resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
			 <&gcc GCC_USB3_PHY_SEC_BCR>;
		reset-names = "phy", "common";

		lane@88eb200 {
			reg = <0x88eb200 0x128>,
			      <0x88eb400 0x1fc>,
			      <0x88eb800 0x218>,
			      <0x88eb600 0x70>;
			#clock-cells = <0>;
			#phy-cells = <0>;
			clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
			clock-names = "pipe0";
			clock-output-names = "usb3_uni_phy_pipe_clk_src";
		};
	};

	phy@1d87000 {
		compatible = "qcom,sdm845-qmp-ufs-phy";
		reg = <0x1d87000 0x18c>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		clock-names = "ref",
			      "ref_aux";
		clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
			 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

		lanes@1d87400 {
			reg = <0x1d87400 0x108>,
			      <0x1d87600 0x1e0>,
			      <0x1d87c00 0x1dc>,
			      <0x1d87800 0x108>,
			      <0x1d87a00 0x1e0>;
			#phy-cells = <0>;
		};
	};
Commit	Line	Data
3a9d31cd VG	1	Qualcomm QMP PHY controller
	2	===========================
	3
	4	QMP phy controller supports physical layer functionality for a number of
	5	controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
	6
	7	Required properties:
	8	- compatible: compatible list, contains:
2d66eab1	9	"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
3a9d31cd	10	"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
0347f0dc	11	"qcom,msm8996-qmp-ufs-phy" for 14nm UFS phy on msm8996,
8587b220	12	"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
0ade2930	13	"qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
d28ffb42	14	"qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
513eff7f	15	"qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
6e256a79 BA	16	"qcom,sdm845-qhp-pcie-phy" for QHP PCIe phy on sdm845,
6e256a79 BA	17	"qcom,sdm845-qmp-pcie-phy" for QMP PCIe phy on sdm845,
7f080207	18	"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
99c7c736	19	"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
76126f5b VK	20	"qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845,
76126f5b VK	21	"qcom,sm8150-qmp-ufs-phy" for UFS QMP phy on sm8150.
3a9d31cd	22
2f2ce8fe DA	23	- reg:
	24	- index 0: address and length of register set for PHY's common
	25	serdes block.
	26	- index 1: address and length of the DP_COM control block (for
	27	"qcom,sdm845-qmp-usb3-phy" only).
	28
	29	- reg-names:
	30	- For "qcom,sdm845-qmp-usb3-phy":
	31	- Should be: "reg-base", "dp_com"
	32	- For all others:
	33	- The reg-names property shouldn't be defined.
3a9d31cd	34
3a9d31cd VG	35	- #address-cells: must be 1
	36	- #size-cells: must be 1
	37	- ranges: must be present
	38
	39	- clocks: a list of phandles and clock-specifier pairs,
	40	one for each entry in clock-names.
	41	- clock-names: "cfg_ahb" for phy config clock,
	42	"aux" for phy aux clock,
	43	"ref" for 19.2 MHz ref clk,
8587b220	44	"com_aux" for phy common block aux clock,
99c7c736	45	"ref_aux" for phy reference aux clock,
7243ec72 DA	46
7243ec72 DA	47	For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
3a9d31cd VG	48	For "qcom,msm8996-qmp-pcie-phy" must contain:
3a9d31cd VG	49	"aux", "cfg_ahb", "ref".
0347f0dc BA	50	For "qcom,msm8996-qmp-ufs-phy" must contain:
0347f0dc BA	51	"ref".
3a9d31cd VG	52	For "qcom,msm8996-qmp-usb3-phy" must contain:
3a9d31cd VG	53	"aux", "cfg_ahb", "ref".
0ade2930 JH	54	For "qcom,msm8998-qmp-usb3-phy" must contain:
0ade2930 JH	55	"aux", "cfg_ahb", "ref".
d28ffb42 MG	56	For "qcom,msm8998-qmp-ufs-phy" must contain:
d28ffb42 MG	57	"ref", "ref_aux".
513eff7f MG	58	For "qcom,msm8998-qmp-pcie-phy" must contain:
513eff7f MG	59	"aux", "cfg_ahb", "ref".
6e256a79 BA	60	For "qcom,sdm845-qhp-pcie-phy" must contain:
	61	"aux", "cfg_ahb", "ref", "refgen".
	62	For "qcom,sdm845-qmp-pcie-phy" must contain:
	63	"aux", "cfg_ahb", "ref", "refgen".
7243ec72 DA	64	For "qcom,sdm845-qmp-usb3-phy" must contain:
	65	"aux", "cfg_ahb", "ref", "com_aux".
	66	For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
8587b220	67	"aux", "cfg_ahb", "ref", "com_aux".
7243ec72 DA	68	For "qcom,sdm845-qmp-ufs-phy" must contain:
7243ec72 DA	69	"ref", "ref_aux".
76126f5b VK	70	For "qcom,sm8150-qmp-ufs-phy" must contain:
76126f5b VK	71	"ref", "ref_aux".
3a9d31cd VG	72
	73	- resets: a list of phandles and reset controller specifier pairs,
	74	one for each entry in reset-names.
	75	- reset-names: "phy" for reset of phy block,
	76	"common" for phy common block reset,
95cee0b4 EG	77	"cfg" for phy's ahb cfg block reset,
95cee0b4 EG	78	"ufsphy" for the PHY reset in the UFS controller.
7243ec72 DA	79
	80	For "qcom,ipq8074-qmp-pcie-phy" must contain:
	81	"phy", "common".
3a9d31cd	82	For "qcom,msm8996-qmp-pcie-phy" must contain:
7243ec72	83	"phy", "common", "cfg".
0347f0dc BA	84	For "qcom,msm8996-qmp-ufs-phy": must contain:
0347f0dc BA	85	"ufsphy".
3a9d31cd	86	For "qcom,msm8996-qmp-usb3-phy" must contain
7243ec72	87	"phy", "common".
0ade2930 JH	88	For "qcom,msm8998-qmp-usb3-phy" must contain
0ade2930 JH	89	"phy", "common".
70831071 MG	90	For "qcom,msm8998-qmp-ufs-phy": must contain:
70831071 MG	91	"ufsphy".
513eff7f MG	92	For "qcom,msm8998-qmp-pcie-phy" must contain:
513eff7f MG	93	"phy", "common".
6e256a79 BA	94	For "qcom,sdm845-qhp-pcie-phy" must contain:
	95	"phy".
	96	For "qcom,sdm845-qmp-pcie-phy" must contain:
	97	"phy".
7243ec72 DA	98	For "qcom,sdm845-qmp-usb3-phy" must contain:
	99	"phy", "common".
	100	For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
	101	"phy", "common".
95cee0b4 EG	102	For "qcom,sdm845-qmp-ufs-phy": must contain:
95cee0b4 EG	103	"ufsphy".
76126f5b VK	104	For "qcom,sm8150-qmp-ufs-phy": must contain:
76126f5b VK	105	"ufsphy".
3a9d31cd VG	106
	107	- vdda-phy-supply: Phandle to a regulator supply to PHY core block.
	108	- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
	109
	110	Optional properties:
	111	- vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
	112	pll block.
	113
	114	Required nodes:
	115	- Each device node of QMP phy is required to have as many child nodes as
	116	the number of lanes the PHY has.
	117
2517d09b	118	Required properties for child nodes of PCIe PHYs (one child per lane):
3a9d31cd	119	- reg: list of offset and length pairs of register sets for PHY blocks -
2517d09b EG	120	tx, rx, pcs, and pcs_misc (optional).
2517d09b EG	121	- #phy-cells: must be 0
3a9d31cd	122
2517d09b EG	123	Required properties for a single "lanes" child node of non-PCIe PHYs:
	124	- reg: list of offset and length pairs of register sets for PHY blocks
	125	For 1-lane devices:
	126	tx, rx, pcs, and (optionally) pcs_misc
	127	For 2-lane devices:
	128	tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
3a9d31cd VG	129	- #phy-cells: must be 0
3a9d31cd VG	130
2517d09b	131	Required properties for child node of PCIe and USB3 qmp phys:
3a9d31cd VG	132	- clocks: a list of phandles and clock-specifier pairs,
3a9d31cd VG	133	one for each entry in clock-names.
7243ec72	134	- clock-names: Must contain following:
3a9d31cd	135	"pipe<lane-number>" for pipe clock specific to each lane.
e88432e7 VN	136	- clock-output-names: Name of the PHY clock that will be the parent for
e88432e7 VN	137	the above pipe clock.
2d66eab1 VN	138	For "qcom,ipq8074-qmp-pcie-phy":
	139	- "pcie20_phy0_pipe_clk" Pipe Clock parent
	140	(or)
	141	"pcie20_phy1_pipe_clk"
d21aafe9 EG	142	- #clock-cells: must be 0
	143	- Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
	144	gate-controlled by the gcc.
2d66eab1	145
7243ec72 DA	146	Required properties for child node of PHYs with lane reset, AKA:
7243ec72 DA	147	"qcom,msm8996-qmp-pcie-phy"
3a9d31cd VG	148	- resets: a list of phandles and reset controller specifier pairs,
3a9d31cd VG	149	one for each entry in reset-names.
7243ec72	150	- reset-names: Must contain following:
3a9d31cd VG	151	"lane<lane-number>" for reset specific to each lane.
	152
	153	Example:
	154	phy@34000 {
	155	compatible = "qcom,msm8996-qmp-pcie-phy";
	156	reg = <0x34000 0x488>;
3a9d31cd VG	157	#address-cells = <1>;
	158	#size-cells = <1>;
	159	ranges;
	160
	161	clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
	162	<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
	163	<&gcc GCC_PCIE_CLKREF_CLK>;
	164	clock-names = "aux", "cfg_ahb", "ref";
	165
	166	vdda-phy-supply = <&pm8994_l28>;
	167	vdda-pll-supply = <&pm8994_l12>;
	168
	169	resets = <&gcc GCC_PCIE_PHY_BCR>,
	170	<&gcc GCC_PCIE_PHY_COM_BCR>,
	171	<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
	172	reset-names = "phy", "common", "cfg";
	173
	174	pciephy_0: lane@35000 {
	175	reg = <0x35000 0x130>,
	176	<0x35200 0x200>,
	177	<0x35400 0x1dc>;
d21aafe9	178	#clock-cells = <0>;
3a9d31cd VG	179	#phy-cells = <0>;
	180
	181	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
	182	clock-names = "pipe0";
e88432e7	183	clock-output-names = "pcie_0_pipe_clk_src";
3a9d31cd VG	184	resets = <&gcc GCC_PCIE_0_PHY_BCR>;
	185	reset-names = "lane0";
	186	};
	187
	188	pciephy_1: lane@36000 {
	189	...
	190	...
	191	};
2517d09b EG	192
	193	phy@88eb000 {
	194	compatible = "qcom,sdm845-qmp-usb3-uni-phy";
	195	reg = <0x88eb000 0x18c>;
2517d09b EG	196	#address-cells = <1>;
	197	#size-cells = <1>;
	198	ranges;
	199
	200	clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
	201	<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	202	<&gcc GCC_USB3_SEC_CLKREF_CLK>,
	203	<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
	204	clock-names = "aux", "cfg_ahb", "ref", "com_aux";
	205
	206	resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
	207	<&gcc GCC_USB3_PHY_SEC_BCR>;
	208	reset-names = "phy", "common";
	209
	210	lane@88eb200 {
	211	reg = <0x88eb200 0x128>,
	212	<0x88eb400 0x1fc>,
	213	<0x88eb800 0x218>,
	214	<0x88eb600 0x70>;
d21aafe9	215	#clock-cells = <0>;
2517d09b EG	216	#phy-cells = <0>;
	217	clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
	218	clock-names = "pipe0";
	219	clock-output-names = "usb3_uni_phy_pipe_clk_src";
	220	};
	221	};
	222
	223	phy@1d87000 {
	224	compatible = "qcom,sdm845-qmp-ufs-phy";
	225	reg = <0x1d87000 0x18c>;
	226	#address-cells = <1>;
	227	#size-cells = <1>;
	228	ranges;
	229	clock-names = "ref",
	230	"ref_aux";
	231	clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
	232	<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
	233
	234	lanes@1d87400 {
	235	reg = <0x1d87400 0x108>,
	236	<0x1d87600 0x1e0>,
	237	<0x1d87c00 0x1dc>,
	238	<0x1d87800 0x108>,
	239	<0x1d87a00 0x1e0>;
	240	#phy-cells = <0>;
	241	};
	242	};