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ccf51c1c SM |
1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
2 | ||
3 | %YAML 1.2 | |
4 | --- | |
5 | $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" | |
6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | |
7 | ||
8 | title: Qualcomm QMP PHY controller | |
9 | ||
10 | maintainers: | |
11 | - Manu Gautam <mgautam@codeaurora.org> | |
12 | ||
13 | description: | |
14 | QMP phy controller supports physical layer functionality for a number of | |
15 | controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. | |
16 | ||
17 | properties: | |
18 | compatible: | |
19 | enum: | |
20 | - qcom,ipq8074-qmp-pcie-phy | |
06657151 | 21 | - qcom,ipq8074-qmp-usb3-phy |
ccf51c1c SM |
22 | - qcom,msm8996-qmp-pcie-phy |
23 | - qcom,msm8996-qmp-ufs-phy | |
24 | - qcom,msm8996-qmp-usb3-phy | |
25 | - qcom,msm8998-qmp-pcie-phy | |
26 | - qcom,msm8998-qmp-ufs-phy | |
27 | - qcom,msm8998-qmp-usb3-phy | |
28 | - qcom,sdm845-qhp-pcie-phy | |
29 | - qcom,sdm845-qmp-pcie-phy | |
30 | - qcom,sdm845-qmp-ufs-phy | |
ccf51c1c SM |
31 | - qcom,sdm845-qmp-usb3-uni-phy |
32 | - qcom,sm8150-qmp-ufs-phy | |
33 | - qcom,sm8250-qmp-ufs-phy | |
34 | ||
35 | reg: | |
ccf51c1c SM |
36 | items: |
37 | - description: Address and length of PHY's common serdes block. | |
ccf51c1c SM |
38 | |
39 | "#clock-cells": | |
f516fb70 | 40 | enum: [ 1, 2 ] |
ccf51c1c SM |
41 | |
42 | "#address-cells": | |
43 | enum: [ 1, 2 ] | |
44 | ||
45 | "#size-cells": | |
46 | enum: [ 1, 2 ] | |
47 | ||
c0eca14c RH |
48 | ranges: true |
49 | ||
ccf51c1c SM |
50 | clocks: |
51 | minItems: 1 | |
52 | maxItems: 4 | |
53 | ||
54 | clock-names: | |
55 | minItems: 1 | |
56 | maxItems: 4 | |
57 | ||
58 | resets: | |
59 | minItems: 1 | |
60 | maxItems: 3 | |
61 | ||
62 | reset-names: | |
63 | minItems: 1 | |
64 | maxItems: 3 | |
65 | ||
66 | vdda-phy-supply: | |
67 | description: | |
f516fb70 | 68 | Phandle to a regulator supply to PHY core block. |
ccf51c1c SM |
69 | |
70 | vdda-pll-supply: | |
71 | description: | |
f516fb70 | 72 | Phandle to 1.8V regulator supply to PHY refclk pll block. |
ccf51c1c SM |
73 | |
74 | vddp-ref-clk-supply: | |
75 | description: | |
f516fb70 | 76 | Phandle to a regulator supply to any specific refclk pll block. |
ccf51c1c SM |
77 | |
78 | #Required nodes: | |
79 | patternProperties: | |
80 | "^phy@[0-9a-f]+$": | |
81 | type: object | |
82 | description: | |
83 | Each device node of QMP phy is required to have as many child nodes as | |
84 | the number of lanes the PHY has. | |
85 | ||
86 | required: | |
87 | - compatible | |
88 | - reg | |
89 | - "#clock-cells" | |
90 | - "#address-cells" | |
91 | - "#size-cells" | |
c0eca14c | 92 | - ranges |
ccf51c1c SM |
93 | - clocks |
94 | - clock-names | |
95 | - resets | |
96 | - reset-names | |
97 | - vdda-phy-supply | |
98 | - vdda-pll-supply | |
99 | ||
100 | additionalProperties: false | |
101 | ||
102 | allOf: | |
103 | - if: | |
104 | properties: | |
105 | compatible: | |
106 | contains: | |
107 | enum: | |
ccf51c1c SM |
108 | - qcom,sdm845-qmp-usb3-uni-phy |
109 | then: | |
110 | properties: | |
111 | clocks: | |
112 | items: | |
113 | - description: Phy aux clock. | |
114 | - description: Phy config clock. | |
115 | - description: 19.2 MHz ref clk. | |
116 | - description: Phy common block aux clock. | |
117 | clock-names: | |
118 | items: | |
119 | - const: aux | |
120 | - const: cfg_ahb | |
121 | - const: ref | |
122 | - const: com_aux | |
123 | resets: | |
124 | items: | |
125 | - description: reset of phy block. | |
126 | - description: phy common block reset. | |
127 | reset-names: | |
128 | items: | |
129 | - const: phy | |
130 | - const: common | |
131 | - if: | |
132 | properties: | |
133 | compatible: | |
134 | contains: | |
135 | enum: | |
136 | - qcom,msm8996-qmp-pcie-phy | |
137 | then: | |
138 | properties: | |
139 | clocks: | |
140 | items: | |
141 | - description: Phy aux clock. | |
142 | - description: Phy config clock. | |
143 | - description: 19.2 MHz ref clk. | |
144 | clock-names: | |
145 | items: | |
146 | - const: aux | |
147 | - const: cfg_ahb | |
148 | - const: ref | |
149 | resets: | |
150 | items: | |
151 | - description: reset of phy block. | |
152 | - description: phy common block reset. | |
153 | - description: phy's ahb cfg block reset. | |
154 | reset-names: | |
155 | items: | |
156 | - const: phy | |
157 | - const: common | |
158 | - const: cfg | |
159 | - if: | |
160 | properties: | |
161 | compatible: | |
162 | contains: | |
163 | enum: | |
06657151 | 164 | - qcom,ipq8074-qmp-usb3-phy |
ccf51c1c SM |
165 | - qcom,msm8996-qmp-usb3-phy |
166 | - qcom,msm8998-qmp-pcie-phy | |
167 | - qcom,msm8998-qmp-usb3-phy | |
168 | then: | |
169 | properties: | |
170 | clocks: | |
171 | items: | |
172 | - description: Phy aux clock. | |
173 | - description: Phy config clock. | |
174 | - description: 19.2 MHz ref clk. | |
175 | clock-names: | |
176 | items: | |
177 | - const: aux | |
178 | - const: cfg_ahb | |
179 | - const: ref | |
180 | resets: | |
181 | items: | |
182 | - description: reset of phy block. | |
183 | - description: phy common block reset. | |
184 | reset-names: | |
185 | items: | |
f516fb70 RH |
186 | - const: phy |
187 | - const: common | |
ccf51c1c SM |
188 | - if: |
189 | properties: | |
190 | compatible: | |
191 | contains: | |
192 | enum: | |
193 | - qcom,msm8996-qmp-ufs-phy | |
194 | then: | |
195 | properties: | |
196 | clocks: | |
197 | items: | |
198 | - description: 19.2 MHz ref clk. | |
199 | clock-names: | |
200 | items: | |
201 | - const: ref | |
202 | resets: | |
203 | items: | |
204 | - description: PHY reset in the UFS controller. | |
205 | reset-names: | |
206 | items: | |
207 | - const: ufsphy | |
208 | - if: | |
209 | properties: | |
210 | compatible: | |
211 | contains: | |
212 | enum: | |
213 | - qcom,msm8998-qmp-ufs-phy | |
214 | - qcom,sdm845-qmp-ufs-phy | |
215 | - qcom,sm8150-qmp-ufs-phy | |
216 | - qcom,sm8250-qmp-ufs-phy | |
217 | then: | |
218 | properties: | |
219 | clocks: | |
220 | items: | |
221 | - description: 19.2 MHz ref clk. | |
222 | - description: Phy reference aux clock. | |
223 | clock-names: | |
224 | items: | |
225 | - const: ref | |
226 | - const: ref_aux | |
227 | resets: | |
228 | items: | |
229 | - description: PHY reset in the UFS controller. | |
230 | reset-names: | |
231 | items: | |
232 | - const: ufsphy | |
233 | - if: | |
234 | properties: | |
235 | compatible: | |
236 | contains: | |
237 | enum: | |
238 | - qcom,ipq8074-qmp-pcie-phy | |
239 | then: | |
240 | properties: | |
241 | clocks: | |
242 | items: | |
243 | - description: pipe clk. | |
244 | clock-names: | |
245 | items: | |
246 | - const: pipe_clk | |
247 | resets: | |
248 | items: | |
249 | - description: reset of phy block. | |
250 | - description: phy common block reset. | |
251 | reset-names: | |
252 | items: | |
253 | - const: phy | |
254 | - const: common | |
255 | - if: | |
256 | properties: | |
257 | compatible: | |
258 | contains: | |
259 | enum: | |
260 | - qcom,sdm845-qhp-pcie-phy | |
261 | - qcom,sdm845-qmp-pcie-phy | |
262 | then: | |
263 | properties: | |
264 | clocks: | |
265 | items: | |
266 | - description: Phy aux clock. | |
267 | - description: Phy config clock. | |
268 | - description: 19.2 MHz ref clk. | |
269 | - description: Phy refgen clk. | |
270 | clock-names: | |
271 | items: | |
272 | - const: aux | |
273 | - const: cfg_ahb | |
274 | - const: ref | |
275 | - const: refgen | |
276 | resets: | |
277 | items: | |
278 | - description: reset of phy block. | |
279 | reset-names: | |
280 | items: | |
281 | - const: phy | |
ccf51c1c SM |
282 | |
283 | examples: | |
284 | - | | |
285 | #include <dt-bindings/clock/qcom,gcc-sdm845.h> | |
59351049 SM |
286 | usb_2_qmpphy: phy-wrapper@88eb000 { |
287 | compatible = "qcom,sdm845-qmp-usb3-uni-phy"; | |
c0eca14c | 288 | reg = <0x088eb000 0x18c>; |
ccf51c1c | 289 | #clock-cells = <1>; |
c0eca14c RH |
290 | #address-cells = <1>; |
291 | #size-cells = <1>; | |
292 | ranges = <0x0 0x088eb000 0x2000>; | |
ccf51c1c | 293 | |
59351049 | 294 | clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >, |
ccf51c1c | 295 | <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
59351049 SM |
296 | <&gcc GCC_USB3_SEC_CLKREF_CLK>, |
297 | <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; | |
ccf51c1c SM |
298 | clock-names = "aux", "cfg_ahb", "ref", "com_aux"; |
299 | ||
59351049 SM |
300 | resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, |
301 | <&gcc GCC_USB3_PHY_SEC_BCR>; | |
ccf51c1c SM |
302 | reset-names = "phy", "common"; |
303 | ||
304 | vdda-phy-supply = <&vdda_usb2_ss_1p2>; | |
305 | vdda-pll-supply = <&vdda_usb2_ss_core>; | |
306 | ||
c0eca14c RH |
307 | usb_2_ssphy: phy@200 { |
308 | reg = <0x200 0x128>, | |
309 | <0x400 0x1fc>, | |
310 | <0x800 0x218>, | |
311 | <0x600 0x70>; | |
ccf51c1c SM |
312 | #clock-cells = <0>; |
313 | #phy-cells = <0>; | |
59351049 | 314 | clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; |
ccf51c1c | 315 | clock-names = "pipe0"; |
59351049 | 316 | clock-output-names = "usb3_uni_phy_pipe_clk_src"; |
ccf51c1c SM |
317 | }; |
318 | }; |