Commit | Line | Data |
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0c4ffcfe MK |
1 | TI Keystone PCIe interface |
2 | ||
96291d56 BH |
3 | Keystone PCI host Controller is based on the Synopsys DesignWare PCI |
4 | hardware version 3.65. It shares common functions with the PCIe DesignWare | |
5 | core driver and inherits common properties defined in | |
e5ca4259 | 6 | Documentation/devicetree/bindings/pci/designware-pcie.txt |
0c4ffcfe | 7 | |
e5ca4259 | 8 | Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt |
96291d56 | 9 | for the details of DesignWare DT bindings. Additional properties are |
0c4ffcfe MK |
10 | described here as well as properties that are not applicable. |
11 | ||
12 | Required Properties:- | |
13 | ||
162aaa3b KVA |
14 | compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC |
15 | Should be "ti,am654-pcie-rc" for RC on AM654x SoC | |
47fe9441 KVA |
16 | reg: Three register ranges as listed in the reg-names property |
17 | reg-names: "dbics" for the DesignWare PCIe registers, "app" for the | |
18 | TI specific application registers, "config" for the | |
19 | configuration space address | |
0c4ffcfe MK |
20 | |
21 | pcie_msi_intc : Interrupt controller device node for MSI IRQ chip | |
22 | interrupt-cells: should be set to 1 | |
0c4ffcfe | 23 | interrupts: GIC interrupt lines connected to PCI MSI interrupt lines |
162aaa3b KVA |
24 | (required if the compatible is "ti,keystone-pcie") |
25 | msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt | |
26 | (required if the compatible is "ti,am654-pcie-rc". | |
0c4ffcfe | 27 | |
03d17838 KVA |
28 | ti,syscon-pcie-id : phandle to the device control module required to set device |
29 | id and vendor id. | |
1c55c426 KVA |
30 | ti,syscon-pcie-mode : phandle to the device control module required to configure |
31 | PCI in either RC mode or EP mode. | |
03d17838 | 32 | |
0c4ffcfe MK |
33 | Example: |
34 | pcie_msi_intc: msi-interrupt-controller { | |
35 | interrupt-controller; | |
36 | #interrupt-cells = <1>; | |
37 | interrupt-parent = <&gic>; | |
38 | interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, | |
39 | <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, | |
40 | <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, | |
41 | <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, | |
42 | <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, | |
43 | <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, | |
44 | <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, | |
45 | <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; | |
46 | }; | |
47 | ||
48 | pcie_intc: Interrupt controller device node for Legacy IRQ chip | |
49 | interrupt-cells: should be set to 1 | |
0c4ffcfe MK |
50 | |
51 | Example: | |
52 | pcie_intc: legacy-interrupt-controller { | |
53 | interrupt-controller; | |
54 | #interrupt-cells = <1>; | |
55 | interrupt-parent = <&gic>; | |
56 | interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, | |
57 | <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, | |
58 | <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, | |
59 | <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; | |
60 | }; | |
61 | ||
62 | Optional properties:- | |
96291d56 BH |
63 | phys: phandle to generic Keystone SerDes PHY for PCI |
64 | phy-names: name of the generic Keystone SerDes PHY for PCI | |
0c4ffcfe MK |
65 | - If boot loader already does PCI link establishment, then phys and |
66 | phy-names shouldn't be present. | |
025dd3da | 67 | interrupts: platform interrupt for error interrupts. |
0c4ffcfe | 68 | |
96291d56 | 69 | DesignWare DT Properties not applicable for Keystone PCI |
0c4ffcfe MK |
70 | |
71 | 1. pcie_bus clock-names not used. Instead, a phandle to phys is used. |