Commit | Line | Data |
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0c4ffcfe MK |
1 | TI Keystone PCIe interface |
2 | ||
3 | Keystone PCI host Controller is based on Designware PCI h/w version 3.65. | |
4 | It shares common functions with PCIe Designware core driver and inherit | |
5 | common properties defined in | |
6 | Documentation/devicetree/bindings/pci/designware-pci.txt | |
7 | ||
8 | Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt | |
9 | for the details of Designware DT bindings. Additional properties are | |
10 | described here as well as properties that are not applicable. | |
11 | ||
12 | Required Properties:- | |
13 | ||
14 | compatibility: "ti,keystone-pcie" | |
15 | reg: index 1 is the base address and length of DW application registers. | |
4455efc9 | 16 | index 2 is the base address and length of PCI device ID register. |
0c4ffcfe MK |
17 | |
18 | pcie_msi_intc : Interrupt controller device node for MSI IRQ chip | |
19 | interrupt-cells: should be set to 1 | |
20 | interrupt-parent: Parent interrupt controller phandle | |
21 | interrupts: GIC interrupt lines connected to PCI MSI interrupt lines | |
22 | ||
23 | Example: | |
24 | pcie_msi_intc: msi-interrupt-controller { | |
25 | interrupt-controller; | |
26 | #interrupt-cells = <1>; | |
27 | interrupt-parent = <&gic>; | |
28 | interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, | |
29 | <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, | |
30 | <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, | |
31 | <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, | |
32 | <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, | |
33 | <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, | |
34 | <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, | |
35 | <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; | |
36 | }; | |
37 | ||
38 | pcie_intc: Interrupt controller device node for Legacy IRQ chip | |
39 | interrupt-cells: should be set to 1 | |
40 | interrupt-parent: Parent interrupt controller phandle | |
41 | interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines | |
42 | ||
43 | Example: | |
44 | pcie_intc: legacy-interrupt-controller { | |
45 | interrupt-controller; | |
46 | #interrupt-cells = <1>; | |
47 | interrupt-parent = <&gic>; | |
48 | interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, | |
49 | <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, | |
50 | <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, | |
51 | <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; | |
52 | }; | |
53 | ||
54 | Optional properties:- | |
55 | phys: phandle to Generic Keystone SerDes phy for PCI | |
56 | phy-names: name of the Generic Keystine SerDes phy for PCI | |
57 | - If boot loader already does PCI link establishment, then phys and | |
58 | phy-names shouldn't be present. | |
025dd3da | 59 | interrupts: platform interrupt for error interrupts. |
0c4ffcfe MK |
60 | |
61 | Designware DT Properties not applicable for Keystone PCI | |
62 | ||
63 | 1. pcie_bus clock-names not used. Instead, a phandle to phys is used. | |
64 |