Commit | Line | Data |
---|---|---|
96291d56 | 1 | * Synopsys DesignWare PCIe interface |
340cba60 JH |
2 | |
3 | Required properties: | |
467c7a73 GP |
4 | - compatible: |
5 | "snps,dw-pcie" for RC mode; | |
71918e24 | 6 | "snps,dw-pcie-ep" for EP mode; |
26f51e85 KVA |
7 | - reg: For designware cores version < 4.80 contains the configuration |
8 | address space. For designware core version >= 4.80, contains | |
9 | the configuration and ATU address space | |
10 | - reg-names: Must be "config" for the PCIe configuration space and "atu" for | |
11 | the ATU address space. | |
4dd964df KVA |
12 | (The old way of getting the configuration address space from "ranges" |
13 | is deprecated and should be avoided.) | |
b12befec KVA |
14 | - num-lanes: number of lanes to use |
15 | RC mode: | |
340cba60 JH |
16 | - #address-cells: set to <3> |
17 | - #size-cells: set to <2> | |
18 | - device_type: set to "pci" | |
19 | - ranges: ranges for the PCI memory and I/O regions | |
20 | - #interrupt-cells: set to <1> | |
b12befec KVA |
21 | - interrupt-map-mask and interrupt-map: standard PCI |
22 | properties to define the mapping of the PCIe interface to interrupt | |
340cba60 | 23 | numbers. |
b12befec | 24 | EP mode: |
96291d56 BH |
25 | - num-ib-windows: number of inbound address translation windows |
26 | - num-ob-windows: number of outbound address translation windows | |
c28f8a1f MV |
27 | |
28 | Optional properties: | |
907fce09 GP |
29 | - num-lanes: number of lanes to use (this property should be specified unless |
30 | the link is brought already up in BIOS) | |
96291d56 | 31 | - reset-gpio: GPIO pin number of power good signal |
df770162 BS |
32 | - clocks: Must contain an entry for each entry in clock-names. |
33 | See ../clocks/clock-bindings.txt for details. | |
34 | - clock-names: Must include the following entries: | |
35 | - "pcie" | |
36 | - "pcie_bus" | |
b12befec | 37 | RC mode: |
96291d56 BH |
38 | - num-viewport: number of view ports configured in hardware. If a platform |
39 | does not specify it, the driver assumes 2. | |
40 | - bus-range: PCI bus numbers covered (it is recommended for new devicetrees | |
41 | to specify this property, to keep backwards compatibility a range of | |
42 | 0x00-0xff is assumed if not present) | |
43 | ||
b12befec | 44 | EP mode: |
96291d56 | 45 | - max-functions: maximum number of functions that can be configured |
5a3aa2a8 JP |
46 | |
47 | Example configuration: | |
48 | ||
467c7a73 | 49 | pcie: pcie@dfc00000 { |
5a3aa2a8 | 50 | compatible = "snps,dw-pcie"; |
467c7a73 GP |
51 | reg = <0xdfc00000 0x0001000>, /* IP registers */ |
52 | <0xd0000000 0x0002000>; /* Configuration space */ | |
53 | reg-names = "dbi", "config"; | |
5a3aa2a8 JP |
54 | #address-cells = <3>; |
55 | #size-cells = <2>; | |
56 | device_type = "pci"; | |
57 | ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000 | |
58 | 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; | |
59 | interrupts = <25>, <24>; | |
60 | #interrupt-cells = <1>; | |
61 | num-lanes = <1>; | |
62 | }; | |
71918e24 GP |
63 | or |
64 | pcie: pcie@dfc00000 { | |
65 | compatible = "snps,dw-pcie-ep"; | |
66 | reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ | |
67 | <0xdfc01000 0x0001000>, /* IP registers 2 */ | |
68 | <0xd0000000 0x2000000>; /* Configuration space */ | |
69 | reg-names = "dbi", "dbi2", "addr_space"; | |
70 | num-ib-windows = <6>; | |
71 | num-ob-windows = <2>; | |
72 | num-lanes = <1>; | |
73 | }; |