Merge branches 'pm-cpuidle', 'pm-sleep' and 'pm-powercap'

[linux-block.git] / Documentation / devicetree / bindings / opp / allwinner,sun50i-h6-operating-points.yaml

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner H6 CPU OPP

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  For some SoCs, the CPU frequency subset and voltage value of each
  OPP varies based on the silicon variant in use. Allwinner Process
  Voltage Scaling Tables define the voltage and frequency values based
  on the speedbin blown in the efuse combination.

allOf:
  - $ref: opp-v2-base.yaml#

properties:
  compatible:
    enum:
      - allwinner,sun50i-h6-operating-points
      - allwinner,sun50i-h616-operating-points

  nvmem-cells:
    description: |
      A phandle pointing to a nvmem-cells node representing the efuse
      register that has information about the speedbin that is used
      to select the right frequency/voltage value pair. Please refer
      to the nvmem-cells bindings in
      Documentation/devicetree/bindings/nvmem/nvmem.yaml and also the
      examples below.

  opp-shared: true

required:
  - compatible
  - nvmem-cells

patternProperties:
  "^opp-[0-9]+$":
    type: object

    properties:
      opp-hz: true
      clock-latency-ns: true
      opp-microvolt: true
      opp-supported-hw:
        maxItems: 1
        description:
          A single 32 bit bitmap value, representing compatible HW, one
          bit per speed bin index.

    patternProperties:
      "^opp-microvolt-speed[0-9]$": true

    required:
      - opp-hz

    unevaluatedProperties: false

additionalProperties: false

examples:
  - |
    cpu_opp_table: opp-table {
        compatible = "allwinner,sun50i-h6-operating-points";
        nvmem-cells = <&speedbin_efuse>;
        opp-shared;

        opp-480000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <480000000>;

            opp-microvolt-speed0 = <880000>;
            opp-microvolt-speed1 = <820000>;
            opp-microvolt-speed2 = <800000>;
        };

        opp-1080000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <1080000000>;

            opp-microvolt-speed0 = <1060000>;
            opp-microvolt-speed1 = <880000>;
            opp-microvolt-speed2 = <840000>;
        };

        opp-1488000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <1488000000>;

            opp-microvolt-speed0 = <1160000>;
            opp-microvolt-speed1 = <1000000>;
            opp-microvolt-speed2 = <960000>;
        };
    };

  - |
    opp-table {
        compatible = "allwinner,sun50i-h616-operating-points";
        nvmem-cells = <&speedbin_efuse>;
        opp-shared;

        opp-480000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <480000000>;

            opp-microvolt = <900000>;
            opp-supported-hw = <0x1f>;
        };

        opp-792000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <792000000>;

            opp-microvolt-speed1 = <900000>;
            opp-microvolt-speed4 = <940000>;
            opp-supported-hw = <0x12>;
        };

        opp-1512000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <1512000000>;

            opp-microvolt = <1100000>;
            opp-supported-hw = <0x0a>;
        };
    };

...