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1 | STMicroelectronics SoC DWMAC glue layer controller |
2 | ||
53b26b9b GC |
3 | This file documents differences between the core properties in |
4 | Documentation/devicetree/bindings/net/stmmac.txt | |
5 | and what is needed on STi platforms to program the stmmac glue logic. | |
6 | ||
d15891ca SK |
7 | The device node has following properties. |
8 | ||
9 | Required properties: | |
160e1fd1 | 10 | - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac", |
53b26b9b | 11 | "st,stih407-dwmac", "st,stid127-dwmac". |
9b1a6d36 PG |
12 | - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which |
13 | encompases the glue register, and the offset of the control register. | |
53b26b9b GC |
14 | - st,gmac_en: this is to enable the gmac into a dedicated sysctl control |
15 | register available on STiH407 SoC. | |
53b26b9b | 16 | - pinctrl-0: pin-control for all the MII mode supported. |
d15891ca | 17 | |
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18 | Optional properties: |
19 | - resets : phandle pointing to the system reset controller with correct | |
20 | reset line index for ethernet reset. | |
21 | - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or | |
22 | MAC can generate it. | |
23 | - st,tx-retime-src: This specifies which clk is wired up to the mac for | |
24 | retimeing tx lines. This is totally board dependent and can take one of the | |
25 | posssible values from "txclk", "clk_125" or "clkgen". | |
26 | If not passed, the internal clock will be used by default. | |
27 | - sti-ethclk: this is the phy clock. | |
28 | - sti-clkconf: this is an extra sysconfig register, available in new SoCs, | |
29 | to program the clk retiming. | |
30 | - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g. | |
31 | STiH407. | |
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32 | |
33 | Example: | |
34 | ||
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35 | ethernet0: dwmac@9630000 { |
36 | device_type = "network"; | |
53b26b9b | 37 | compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; |
9b1a6d36 PG |
38 | reg = <0x9630000 0x8000>; |
39 | reg-names = "stmmaceth"; | |
d15891ca | 40 | |
9b1a6d36 | 41 | st,syscon = <&syscfg_sbc_reg 0x80>; |
53b26b9b GC |
42 | st,gmac_en; |
43 | resets = <&softreset STIH407_ETH1_SOFTRESET>; | |
44 | reset-names = "stmmaceth"; | |
d15891ca | 45 | |
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46 | interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, |
47 | <GIC_SPI 99 IRQ_TYPE_NONE>, | |
48 | <GIC_SPI 100 IRQ_TYPE_NONE>; | |
49 | interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; | |
50 | ||
51 | snps,pbl = <32>; | |
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52 | snps,mixed-burst; |
53 | ||
53b26b9b GC |
54 | pinctrl-names = "default"; |
55 | pinctrl-0 = <&pinctrl_rgmii1>; | |
56 | ||
57 | clock-names = "stmmaceth", "sti-ethclk"; | |
58 | clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>, | |
59 | <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>; | |
d15891ca | 60 | }; |