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5b8b6484 LP |
1 | * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC) |
2 | ||
d8256121 | 3 | This binding is deprecated, but it continues to be supported, but new |
4 | features should be preferably added to the stmmac binding document. | |
5 | ||
d4b8e2c5 SW |
6 | This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service) |
7 | IP block. The IP supports multiple options for bus type, clocking and reset | |
8 | structure, and feature list. Consequently, a number of properties and list | |
9 | entries in properties are marked as optional, or only required in specific HW | |
10 | configurations. | |
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11 | |
12 | Required properties: | |
d4b8e2c5 SW |
13 | - compatible: One of: |
14 | - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10" | |
15 | Represents the IP core when integrated into the Axis ARTPEC-6 SoC. | |
16 | - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10" | |
17 | Represents the IP core when integrated into the NVIDIA Tegra186 SoC. | |
18 | - "snps,dwc-qos-ethernet-4.10" | |
19 | This combination is deprecated. It should be treated as equivalent to | |
20 | "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be | |
21 | compatible with earlier revisions of this binding. | |
5b8b6484 | 22 | - reg: Address and length of the register set for the device |
d4b8e2c5 SW |
23 | - clocks: Phandle and clock specifiers for each entry in clock-names, in the |
24 | same order. See ../clock/clock-bindings.txt. | |
25 | - clock-names: May contain any/all of the following depending on the IP | |
26 | configuration, in any order: | |
27 | - "tx" | |
28 | The EQOS transmit path clock. The HW signal name is clk_tx_i. | |
29 | In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX | |
30 | path. In other configurations, other clocks (such as tx_125, rmii) may | |
31 | drive the PHY TX path. | |
32 | - "rx" | |
33 | The EQOS receive path clock. The HW signal name is clk_rx_i. | |
34 | In some configurations (e.g. GMII/RGMII), this clock is derived from the | |
35 | PHY's RX clock output. In other configurations, other clocks (such as | |
36 | rx_125, rmii) may drive the EQOS RX path. | |
37 | In cases where the PHY clock is directly fed into the EQOS receive path | |
38 | without intervening logic, the DT need not represent this clock, since it | |
39 | is assumed to be fully under the control of the PHY device/driver. In | |
40 | cases where SoC integration adds additional logic to this path, such as a | |
41 | SW-controlled clock gate, this clock should be represented in DT. | |
42 | - "slave_bus" | |
43 | The CPU/slave-bus (CSR) interface clock. This applies to any bus type; | |
44 | APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other | |
45 | buses). | |
46 | - "master_bus" | |
47 | The master bus interface clock. Only required in configurations that use a | |
48 | separate clock for the master and slave bus interfaces. The HW signal name | |
49 | is hclk_i (AHB) or aclk_i (AXI). | |
50 | - "ptp_ref" | |
51 | The PTP reference clock. The HW signal name is clk_ptp_ref_i. | |
52 | - "phy_ref_clk" | |
53 | This clock is deprecated and should not be used by new compatible values. | |
54 | It is equivalent to "tx". | |
55 | - "apb_pclk" | |
56 | This clock is deprecated and should not be used by new compatible values. | |
57 | It is equivalent to "slave_bus". | |
58 | ||
59 | Note: Support for additional IP configurations may require adding the | |
60 | following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i, | |
61 | clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i. | |
62 | Configurations exist where multiple similar clocks are used at once, e.g. all | |
63 | of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to | |
64 | extend the binding with a separate clock-names entry for each of those RX | |
65 | clocks, rather than repurposing the existing "rx" clock-names entry as a | |
66 | generic/logical clock in a similar fashion to "master_bus" and "slave_bus". | |
67 | This will allow easy support for configurations that support multiple PHY | |
68 | interfaces using a mux, and hence need to have explicit control over | |
69 | specific RX clocks. | |
70 | ||
71 | The following compatible values require the following set of clocks: | |
72 | - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": | |
73 | - "slave_bus" | |
74 | - "master_bus" | |
75 | - "rx" | |
76 | - "tx" | |
77 | - "ptp_ref" | |
78 | - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": | |
79 | - "slave_bus" | |
80 | - "master_bus" | |
81 | - "tx" | |
82 | - "ptp_ref" | |
83 | - "snps,dwc-qos-ethernet-4.10" (deprecated): | |
84 | - "phy_ref_clk" | |
85 | - "apb_clk" | |
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86 | - interrupt-parent: Should be the phandle for the interrupt controller |
87 | that services interrupts for this device | |
88 | - interrupts: Should contain the core's combined interrupt signal | |
89 | - phy-mode: See ethernet.txt file in the same directory | |
d4b8e2c5 SW |
90 | - resets: Phandle and reset specifiers for each entry in reset-names, in the |
91 | same order. See ../reset/reset.txt. | |
92 | - reset-names: May contain any/all of the following depending on the IP | |
93 | configuration, in any order: | |
94 | - "eqos". The reset to the entire module. The HW signal name is hreset_n | |
95 | (AHB) or aresetn_i (AXI). | |
96 | ||
97 | The following compatible values require the following set of resets: | |
98 | (the reset properties may be omitted if empty) | |
99 | - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": | |
100 | - "eqos". | |
101 | - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": | |
102 | - None. | |
103 | - "snps,dwc-qos-ethernet-4.10" (deprecated): | |
104 | - None. | |
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105 | |
106 | Optional properties: | |
107 | - dma-coherent: Present if dma operations are coherent | |
108 | - mac-address: See ethernet.txt in the same directory | |
109 | - local-mac-address: See ethernet.txt in the same directory | |
d4b8e2c5 SW |
110 | - phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY. |
111 | See ../gpio/gpio.txt. | |
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112 | - snps,en-lpi: If present it enables use of the AXI low-power interface |
113 | - snps,write-requests: Number of write requests that the AXI port can issue. | |
114 | It depends on the SoC configuration. | |
115 | - snps,read-requests: Number of read requests that the AXI port can issue. | |
116 | It depends on the SoC configuration. | |
117 | - snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB | |
118 | representing 4, then 8 etc. | |
119 | - snps,txpbl: DMA Programmable burst length for the TX DMA | |
120 | - snps,rxpbl: DMA Programmable burst length for the RX DMA | |
121 | - snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during | |
122 | TX low-power mode. | |
123 | - phy-handle: See ethernet.txt file in the same directory | |
124 | - mdio device tree subnode: When the GMAC has a phy connected to its local | |
125 | mdio, there must be device tree subnode with the following | |
126 | required properties: | |
127 | - compatible: Must be "snps,dwc-qos-ethernet-mdio". | |
128 | - #address-cells: Must be <1>. | |
129 | - #size-cells: Must be <0>. | |
130 | ||
131 | For each phy on the mdio bus, there must be a node with the following | |
132 | fields: | |
133 | ||
134 | - reg: phy id used to communicate to phy. | |
135 | - device_type: Must be "ethernet-phy". | |
136 | - fixed-mode device tree subnode: see fixed-link.txt in the same directory | |
137 | ||
138 | Examples: | |
139 | ethernet2@40010000 { | |
140 | clock-names = "phy_ref_clk", "apb_pclk"; | |
141 | clocks = <&clkc 17>, <&clkc 15>; | |
142 | compatible = "snps,dwc-qos-ethernet-4.10"; | |
143 | interrupt-parent = <&intc>; | |
144 | interrupts = <0x0 0x1e 0x4>; | |
145 | reg = <0x40010000 0x4000>; | |
146 | phy-handle = <&phy2>; | |
147 | phy-mode = "gmii"; | |
d4b8e2c5 | 148 | phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>; |
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149 | |
150 | snps,en-tx-lpi-clockgating; | |
151 | snps,en-lpi; | |
152 | snps,write-requests = <2>; | |
153 | snps,read-requests = <16>; | |
154 | snps,burst-map = <0x7>; | |
155 | snps,txpbl = <8>; | |
156 | snps,rxpbl = <2>; | |
157 | ||
158 | dma-coherent; | |
159 | ||
160 | mdio { | |
161 | #address-cells = <0x1>; | |
162 | #size-cells = <0x0>; | |
163 | phy2: phy@1 { | |
164 | compatible = "ethernet-phy-ieee802.3-c22"; | |
165 | device_type = "ethernet-phy"; | |
166 | reg = <0x1>; | |
167 | }; | |
168 | }; | |
169 | }; |