projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 53a83930 RC |
1 | Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC) |
| 2 | ||
| 3 | The device node has following properties. | |
| 4 | ||
| 5 | Required properties: | |
| ba289af8 RC |
6 | - compatible: should be "rockchip,<name>-gamc" |
| 7 | "rockchip,rk3228-gmac": found on RK322x SoCs | |
| 8 | "rockchip,rk3288-gmac": found on RK3288 SoCs | |
| d4ff816e | 9 | "rockchip,rk3328-gmac": found on RK3328 SoCs |
| ba289af8 RC |
10 | "rockchip,rk3366-gmac": found on RK3366 SoCs |
| 11 | "rockchip,rk3368-gmac": found on RK3368 SoCs | |
| 12 | "rockchip,rk3399-gmac": found on RK3399 SoCs | |
| 89c9c163 | 13 | "rockchip,rv1108-gmac": found on RV1108 SoCs |
| 53a83930 RC |
14 | - reg: addresses and length of the register sets for the device. |
| 15 | - interrupts: Should contain the GMAC interrupts. | |
| 16 | - interrupt-names: Should contain the interrupt names "macirq". | |
| 17 | - rockchip,grf: phandle to the syscon grf used to control speed and mode. | |
| 18 | - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY. | |
| 19 | <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC | |
| 20 | <&cru SCLK_MAC_RX>: clock gate for RX | |
| 21 | <&cru SCLK_MAC_TX>: clock gate for TX | |
| 22 | <&cru SCLK_MACREF>: clock gate for RMII referce clock | |
| 23 | <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output | |
| 24 | <&cru ACLK_GMAC>: AXI clock gate for GMAC | |
| 25 | <&cru PCLK_GMAC>: APB clock gate for GMAC | |
| 26 | - clock-names: One name for each entry in the clocks property. | |
| 27 | - phy-mode: See ethernet.txt file in the same directory. | |
| 28 | - pinctrl-names: Names corresponding to the numbered pinctrl states. | |
| 29 | - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>. | |
| 30 | - clock_in_out: For RGMII, it must be "input", means main clock(125MHz) | |
| 31 | is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means | |
| 32 | PHY provides the reference clock(50MHz), "output" means GMAC provides the | |
| 33 | reference clock. | |
| 34 | - snps,reset-gpio gpio number for phy reset. | |
| 35 | - snps,reset-active-low boolean flag to indicate if phy reset is active low. | |
| 36 | - assigned-clocks: main clock, should be <&cru SCLK_MAC>; | |
| 37 | - assigned-clock-parents = parent of main clock. | |
| 38 | can be <&ext_gmac> or <&cru SCLK_MAC_PLL>. | |
| 39 | ||
| 40 | Optional properties: | |
| 41 | - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default. | |
| 42 | - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default. | |
| 384dd55d | 43 | - phy-supply: phandle to a regulator if the PHY needs one |
| 53a83930 RC |
44 | |
| 45 | Example: | |
| 46 | ||
| 47 | gmac: ethernet@ff290000 { | |
| 48 | compatible = "rockchip,rk3288-gmac"; | |
| 49 | reg = <0xff290000 0x10000>; | |
| 50 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
| 51 | interrupt-names = "macirq"; | |
| 52 | rockchip,grf = <&grf>; | |
| 53 | clocks = <&cru SCLK_MAC>, | |
| 54 | <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, | |
| 55 | <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, | |
| 56 | <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; | |
| 57 | clock-names = "stmmaceth", | |
| 58 | "mac_clk_rx", "mac_clk_tx", | |
| 59 | "clk_mac_ref", "clk_mac_refout", | |
| 60 | "aclk_mac", "pclk_mac"; | |
| 61 | phy-mode = "rgmii"; | |
| 62 | pinctrl-names = "default"; | |
| 63 | pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>; | |
| 64 | ||
| 65 | clock_in_out = "input"; | |
| 66 | snps,reset-gpio = <&gpio4 7 0>; | |
| 67 | snps,reset-active-low; | |
| 68 | ||
| 69 | assigned-clocks = <&cru SCLK_MAC>; | |
| 70 | assigned-clock-parents = <&ext_gmac>; | |
| 71 | tx_delay = <0x30>; | |
| 72 | rx_delay = <0x10>; | |
| 73 | ||
| 53a83930 | 74 | }; |