[linux-2.6-block.git] / Documentation / devicetree / bindings / net / renesas,ravb.txt

* Renesas Electronics Ethernet AVB

This file provides information on what the device node for the Ethernet AVB
interface contains.

Required properties:
- compatible: Must contain one or more of the following:
      - "renesas,etheravb-r8a7743" for the R8A7743 SoC.
      - "renesas,etheravb-r8a7745" for the R8A7745 SoC.
      - "renesas,etheravb-r8a77470" for the R8A77470 SoC.
      - "renesas,etheravb-r8a7790" for the R8A7790 SoC.
      - "renesas,etheravb-r8a7791" for the R8A7791 SoC.
      - "renesas,etheravb-r8a7792" for the R8A7792 SoC.
      - "renesas,etheravb-r8a7793" for the R8A7793 SoC.
      - "renesas,etheravb-r8a7794" for the R8A7794 SoC.
      - "renesas,etheravb-rcar-gen2" as a fallback for the above
		R-Car Gen2 and RZ/G1 devices.

      - "renesas,etheravb-r8a7795" for the R8A7795 SoC.
      - "renesas,etheravb-r8a7796" for the R8A7796 SoC.
      - "renesas,etheravb-r8a77965" for the R8A77965 SoC.
      - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
      - "renesas,etheravb-r8a77980" for the R8A77980 SoC.
      - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
      - "renesas,etheravb-rcar-gen3" as a fallback for the above
		R-Car Gen3 devices.

	When compatible with the generic version, nodes must list the
	SoC-specific version corresponding to the platform first followed by
	the generic version.

- reg: Offset and length of (1) the register block and (2) the stream buffer.
       The region for the register block is mandatory.
       The region for the stream buffer is optional, as it is only present on
       R-Car Gen2 and RZ/G1 SoCs, and on R-Car H3 (R8A7795), M3-W (R8A7796),
       and M3-N (R8A77965).
- interrupts: A list of interrupt-specifiers, one for each entry in
	      interrupt-names.
	      If interrupt-names is not present, an interrupt specifier
	      for a single muxed interrupt.
- phy-mode: see ethernet.txt file in the same directory.
- phy-handle: see ethernet.txt file in the same directory.
- #address-cells: number of address cells for the MDIO bus, must be equal to 1.
- #size-cells: number of size cells on the MDIO bus, must be equal to 0.
- clocks: clock phandle and specifier pair.
- pinctrl-0: phandle, referring to a default pin configuration node.

Optional properties:
- interrupt-parent: the phandle for the interrupt controller that services
		    interrupts for this device.
- interrupt-names: A list of interrupt names.
		   For the R-Car Gen 3 SoCs this property is mandatory;
		   it should include one entry per channel, named "ch%u",
		   where %u is the channel number ranging from 0 to 24.
		   For other SoCs this property is optional; if present
		   it should contain "mux" for a single muxed interrupt.
- pinctrl-names: pin configuration state name ("default").
- renesas,no-ether-link: boolean, specify when a board does not provide a proper
			 AVB_LINK signal.
- renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
				 active-low instead of normal active-high.

Example:

	ethernet@e6800000 {
		compatible = "renesas,etheravb-r8a7795", "renesas,etheravb-rcar-gen3";
		reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "ch0", "ch1", "ch2", "ch3",
				  "ch4", "ch5", "ch6", "ch7",
				  "ch8", "ch9", "ch10", "ch11",
				  "ch12", "ch13", "ch14", "ch15",
				  "ch16", "ch17", "ch18", "ch19",
				  "ch20", "ch21", "ch22", "ch23",
				  "ch24";
		clocks = <&cpg CPG_MOD 812>;
		power-domains = <&cpg>;
		phy-mode = "rgmii-id";
		phy-handle = <&phy0>;

		pinctrl-0 = <&ether_pins>;
		pinctrl-names = "default";
		renesas,no-ether-link;
		#address-cells = <1>;
		#size-cells = <0>;

		phy0: ethernet-phy@0 {
			rxc-skew-ps = <900>;
			rxdv-skew-ps = <0>;
			rxd0-skew-ps = <0>;
			rxd1-skew-ps = <0>;
			rxd2-skew-ps = <0>;
			rxd3-skew-ps = <0>;
			txc-skew-ps = <900>;
			txen-skew-ps = <0>;
			txd0-skew-ps = <0>;
			txd1-skew-ps = <0>;
			txd2-skew-ps = <0>;
			txd3-skew-ps = <0>;
			reg = <0>;
			interrupt-parent = <&gpio2>;
			interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
		};
	};
Commit	Line	Data
c156633f SS	1	* Renesas Electronics Ethernet AVB
	2
	3	This file provides information on what the device node for the Ethernet AVB
	4	interface contains.
	5
	6	Required properties:
b3a703c7 BD	7	- compatible: Must contain one or more of the following:
b3a703c7 BD	8	- "renesas,etheravb-r8a7743" for the R8A7743 SoC.
22cb7a3a	9	- "renesas,etheravb-r8a7745" for the R8A7745 SoC.
9b857563	10	- "renesas,etheravb-r8a77470" for the R8A77470 SoC.
b3a703c7 BD	11	- "renesas,etheravb-r8a7790" for the R8A7790 SoC.
	12	- "renesas,etheravb-r8a7791" for the R8A7791 SoC.
	13	- "renesas,etheravb-r8a7792" for the R8A7792 SoC.
	14	- "renesas,etheravb-r8a7793" for the R8A7793 SoC.
	15	- "renesas,etheravb-r8a7794" for the R8A7794 SoC.
	16	- "renesas,etheravb-rcar-gen2" as a fallback for the above
	17	R-Car Gen2 and RZ/G1 devices.
0e874361	18
b3a703c7 BD	19	- "renesas,etheravb-r8a7795" for the R8A7795 SoC.
b3a703c7 BD	20	- "renesas,etheravb-r8a7796" for the R8A7796 SoC.
1a862488	21	- "renesas,etheravb-r8a77965" for the R8A77965 SoC.
785ec874	22	- "renesas,etheravb-r8a77970" for the R8A77970 SoC.
3a291aa1	23	- "renesas,etheravb-r8a77980" for the R8A77980 SoC.
f231c417	24	- "renesas,etheravb-r8a77995" for the R8A77995 SoC.
b3a703c7 BD	25	- "renesas,etheravb-rcar-gen3" as a fallback for the above
	26	R-Car Gen3 devices.
	27
	28	When compatible with the generic version, nodes must list the
	29	SoC-specific version corresponding to the platform first followed by
	30	the generic version.
0e874361	31
25b5cdfc GU	32	- reg: Offset and length of (1) the register block and (2) the stream buffer.
	33	The region for the register block is mandatory.
	34	The region for the stream buffer is optional, as it is only present on
	35	R-Car Gen2 and RZ/G1 SoCs, and on R-Car H3 (R8A7795), M3-W (R8A7796),
	36	and M3-N (R8A77965).
619f3bd2 KM	37	- interrupts: A list of interrupt-specifiers, one for each entry in
	38	interrupt-names.
	39	If interrupt-names is not present, an interrupt specifier
	40	for a single muxed interrupt.
c156633f SS	41	- phy-mode: see ethernet.txt file in the same directory.
	42	- phy-handle: see ethernet.txt file in the same directory.
	43	- #address-cells: number of address cells for the MDIO bus, must be equal to 1.
	44	- #size-cells: number of size cells on the MDIO bus, must be equal to 0.
	45	- clocks: clock phandle and specifier pair.
	46	- pinctrl-0: phandle, referring to a default pin configuration node.
	47
	48	Optional properties:
	49	- interrupt-parent: the phandle for the interrupt controller that services
	50	interrupts for this device.
619f3bd2	51	- interrupt-names: A list of interrupt names.
785ec874	52	For the R-Car Gen 3 SoCs this property is mandatory;
619f3bd2 KM	53	it should include one entry per channel, named "ch%u",
	54	where %u is the channel number ranging from 0 to 24.
	55	For other SoCs this property is optional; if present
	56	it should contain "mux" for a single muxed interrupt.
c156633f SS	57	- pinctrl-names: pin configuration state name ("default").
	58	- renesas,no-ether-link: boolean, specify when a board does not provide a proper
	59	AVB_LINK signal.
	60	- renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
	61	active-low instead of normal active-high.
	62
	63	Example:
	64
	65	ethernet@e6800000 {
0e874361	66	compatible = "renesas,etheravb-r8a7795", "renesas,etheravb-rcar-gen3";
619f3bd2	67	reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
c156633f	68	interrupt-parent = <&gic>;
619f3bd2 KM	69	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	70	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	71	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	72	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	73	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	74	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	75	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	76	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	77	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	78	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	79	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	80	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	81	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	82	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	83	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	84	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	85	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	86	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	87	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	88	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	89	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	90	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	91	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	92	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	93	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	94	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	95	"ch4", "ch5", "ch6", "ch7",
	96	"ch8", "ch9", "ch10", "ch11",
	97	"ch12", "ch13", "ch14", "ch15",
	98	"ch16", "ch17", "ch18", "ch19",
	99	"ch20", "ch21", "ch22", "ch23",
	100	"ch24";
705bcdda GU	101	clocks = <&cpg CPG_MOD 812>;
705bcdda GU	102	power-domains = <&cpg>;
619f3bd2	103	phy-mode = "rgmii-id";
c156633f	104	phy-handle = <&phy0>;
619f3bd2	105
c156633f SS	106	pinctrl-0 = <&ether_pins>;
	107	pinctrl-names = "default";
	108	renesas,no-ether-link;
	109	#address-cells = <1>;
	110	#size-cells = <0>;
	111
	112	phy0: ethernet-phy@0 {
619f3bd2 KM	113	rxc-skew-ps = <900>;
	114	rxdv-skew-ps = <0>;
	115	rxd0-skew-ps = <0>;
	116	rxd1-skew-ps = <0>;
	117	rxd2-skew-ps = <0>;
	118	rxd3-skew-ps = <0>;
	119	txc-skew-ps = <900>;
	120	txen-skew-ps = <0>;
	121	txd0-skew-ps = <0>;
	122	txd1-skew-ps = <0>;
	123	txd2-skew-ps = <0>;
	124	txd3-skew-ps = <0>;
c156633f SS	125	reg = <0>;
c156633f SS	126	interrupt-parent = <&gpio2>;
619f3bd2	127	interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
c156633f SS	128	};
c156633f SS	129	};