[linux-2.6-block.git] / Documentation / devicetree / bindings / net / meson-dwmac.txt

* Amlogic Meson DWMAC Ethernet controller

The device inherits all the properties of the dwmac/stmmac devices
described in the file stmmac.txt in the current directory with the
following changes.

Required properties on all platforms:

- compatible:	Depending on the platform this should be one of:
			- "amlogic,meson6-dwmac"
			- "amlogic,meson8b-dwmac"
			- "amlogic,meson-gxbb-dwmac"
		Additionally "snps,dwmac" and any applicable more
		detailed version number described in net/stmmac.txt
		should be used.

- reg:	The first register range should be the one of the DWMAC
	controller. The second range is is for the Amlogic specific
	configuration (for example the PRG_ETHERNET register range
	on Meson8b and newer)

Required properties on Meson8b and newer:
- clock-names:	Should contain the following:
		- "stmmaceth" - see stmmac.txt
		- "clkin0" - first parent clock of the internal mux
		- "clkin1" - second parent clock of the internal mux

Optional properties on Meson8b and newer:
- amlogic,tx-delay-ns:	The internal RGMII TX clock delay (provided
			by this driver) in nanoseconds. Allowed values
			are: 0ns, 2ns, 4ns, 6ns.
			When phy-mode is set to "rgmii" then the TX
			delay should be explicitly configured. When
			not configured a fallback of 2ns is used.
			When the phy-mode is set to either "rgmii-id"
			or "rgmii-txid" the TX clock delay is already
			provided by the PHY. In that case this
			property should be set to 0ns (which disables
			the TX clock delay in the MAC to prevent the
			clock from going off because both PHY and MAC
			are adding a delay).
			Any configuration is ignored when the phy-mode
			is set to "rmii".

Example for Meson6:

	ethmac: ethernet@c9410000 {
		compatible = "amlogic,meson6-dwmac", "snps,dwmac";
		reg = <0xc9410000 0x10000
		       0xc1108108 0x4>;
		interrupts = <0 8 1>;
		interrupt-names = "macirq";
		clocks = <&clk81>;
		clock-names = "stmmaceth";
	}

Example for GXBB:
	ethmac: ethernet@c9410000 {
		compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
		reg = <0x0 0xc9410000 0x0 0x10000>,
			<0x0 0xc8834540 0x0 0x8>;
		interrupts = <0 8 1>;
		interrupt-names = "macirq";
		clocks = <&clkc CLKID_ETH>,
				<&clkc CLKID_FCLK_DIV2>,
				<&clkc CLKID_MPLL2>;
		clock-names = "stmmaceth", "clkin0", "clkin1";
		phy-mode = "rgmii";
	};
Commit	Line	Data
318fd490 BG	1	* Amlogic Meson DWMAC Ethernet controller
	2
	3	The device inherits all the properties of the dwmac/stmmac devices
6aee1597 MB	4	described in the file stmmac.txt in the current directory with the
6aee1597 MB	5	following changes.
318fd490	6
6aee1597	7	Required properties on all platforms:
318fd490	8
6aee1597 MB	9	- compatible: Depending on the platform this should be one of:
	10	- "amlogic,meson6-dwmac"
	11	- "amlogic,meson8b-dwmac"
	12	- "amlogic,meson-gxbb-dwmac"
	13	Additionally "snps,dwmac" and any applicable more
	14	detailed version number described in net/stmmac.txt
	15	should be used.
318fd490	16
6aee1597 MB	17	- reg: The first register range should be the one of the DWMAC
	18	controller. The second range is is for the Amlogic specific
	19	configuration (for example the PRG_ETHERNET register range
	20	on Meson8b and newer)
318fd490	21
6aee1597 MB	22	Required properties on Meson8b and newer:
	23	- clock-names: Should contain the following:
	24	- "stmmaceth" - see stmmac.txt
	25	- "clkin0" - first parent clock of the internal mux
	26	- "clkin1" - second parent clock of the internal mux
	27
d5490f1f MB	28	Optional properties on Meson8b and newer:
	29	- amlogic,tx-delay-ns: The internal RGMII TX clock delay (provided
	30	by this driver) in nanoseconds. Allowed values
	31	are: 0ns, 2ns, 4ns, 6ns.
	32	When phy-mode is set to "rgmii" then the TX
	33	delay should be explicitly configured. When
	34	not configured a fallback of 2ns is used.
	35	When the phy-mode is set to either "rgmii-id"
	36	or "rgmii-txid" the TX clock delay is already
	37	provided by the PHY. In that case this
	38	property should be set to 0ns (which disables
	39	the TX clock delay in the MAC to prevent the
	40	clock from going off because both PHY and MAC
	41	are adding a delay).
	42	Any configuration is ignored when the phy-mode
	43	is set to "rmii".
6aee1597 MB	44
6aee1597 MB	45	Example for Meson6:
318fd490 BG	46
	47	ethmac: ethernet@c9410000 {
	48	compatible = "amlogic,meson6-dwmac", "snps,dwmac";
	49	reg = <0xc9410000 0x10000
	50	0xc1108108 0x4>;
	51	interrupts = <0 8 1>;
	52	interrupt-names = "macirq";
	53	clocks = <&clk81>;
	54	clock-names = "stmmaceth";
	55	}
6aee1597 MB	56
	57	Example for GXBB:
	58	ethmac: ethernet@c9410000 {
	59	compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
	60	reg = <0x0 0xc9410000 0x0 0x10000>,
	61	<0x0 0xc8834540 0x0 0x8>;
	62	interrupts = <0 8 1>;
	63	interrupt-names = "macirq";
	64	clocks = <&clkc CLKID_ETH>,
	65	<&clkc CLKID_FCLK_DIV2>,
	66	<&clkc CLKID_MPLL2>;
	67	clock-names = "stmmaceth", "clkin0", "clkin1";
	68	phy-mode = "rgmii";
6aee1597	69	};