Commit | Line | Data |
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58ff9865 JC |
1 | MediaTek Frame Engine Ethernet controller |
2 | ========================================= | |
3 | ||
4 | The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs | |
5 | have dual GMAC each represented by a child node.. | |
6 | ||
7 | * Ethernet controller node | |
8 | ||
9 | Required properties: | |
10 | - compatible: Should be "mediatek,mt7623-eth" | |
11 | - reg: Address and length of the register set for the device | |
f1d0540d JC |
12 | - interrupts: Should contain the three frame engines interrupts in numeric |
13 | order. These are fe_int0, fe_int1 and fe_int2. | |
58ff9865 JC |
14 | - clocks: the clock used by the core |
15 | - clock-names: the names of the clock listed in the clocks property. These are | |
16 | "ethif", "esw", "gp2", "gp1" | |
17 | - power-domains: phandle to the power domain that the ethernet is part of | |
18 | - resets: Should contain a phandle to the ethsys reset signal | |
19 | - reset-names: Should contain the reset signal name "eth" | |
20 | - mediatek,ethsys: phandle to the syscon node that handles the port setup | |
21 | - mediatek,pctl: phandle to the syscon node that handles the ports slew rate | |
22 | and driver current | |
23 | ||
24 | Optional properties: | |
25 | - interrupt-parent: Should be the phandle for the interrupt controller | |
26 | that services interrupts for this device | |
27 | ||
28 | ||
29 | * Ethernet MAC node | |
30 | ||
31 | Required properties: | |
32 | - compatible: Should be "mediatek,eth-mac" | |
33 | - reg: The number of the MAC | |
34 | - phy-handle: see ethernet.txt file in the same directory. | |
35 | ||
36 | Example: | |
37 | ||
38 | eth: ethernet@1b100000 { | |
39 | compatible = "mediatek,mt7623-eth"; | |
40 | reg = <0 0x1b100000 0 0x20000>; | |
41 | clocks = <&topckgen CLK_TOP_ETHIF_SEL>, | |
42 | <ðsys CLK_ETHSYS_ESW>, | |
43 | <ðsys CLK_ETHSYS_GP2>, | |
44 | <ðsys CLK_ETHSYS_GP1>; | |
45 | clock-names = "ethif", "esw", "gp2", "gp1"; | |
f1d0540d JC |
46 | interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW |
47 | GIC_SPI 199 IRQ_TYPE_LEVEL_LOW | |
48 | GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; | |
58ff9865 JC |
49 | power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; |
50 | resets = <ðsys MT2701_ETHSYS_ETH_RST>; | |
51 | reset-names = "eth"; | |
52 | mediatek,ethsys = <ðsys>; | |
53 | mediatek,pctl = <&syscfg_pctl_a>; | |
54 | #address-cells = <1>; | |
55 | #size-cells = <0>; | |
56 | ||
57 | gmac1: mac@0 { | |
58 | compatible = "mediatek,eth-mac"; | |
59 | reg = <0>; | |
60 | phy-handle = <&phy0>; | |
61 | }; | |
62 | ||
63 | gmac2: mac@1 { | |
64 | compatible = "mediatek,eth-mac"; | |
65 | reg = <1>; | |
66 | phy-handle = <&phy1>; | |
67 | }; | |
68 | ||
69 | mdio-bus { | |
70 | phy0: ethernet-phy@0 { | |
71 | reg = <0>; | |
72 | phy-mode = "rgmii"; | |
73 | }; | |
74 | ||
75 | phy1: ethernet-phy@1 { | |
76 | reg = <1>; | |
77 | phy-mode = "rgmii"; | |
78 | }; | |
79 | }; | |
80 | }; |