[linux-2.6-block.git] / Documentation / devicetree / bindings / net / mediatek-net.txt

MediaTek Frame Engine Ethernet controller
=========================================

The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
have dual GMAC each represented by a child node..

* Ethernet controller node

Required properties:
- compatible: Should be "mediatek,mt7623-eth"
- reg: Address and length of the register set for the device
- interrupts: Should contain the three frame engines interrupts in numeric
	order. These are fe_int0, fe_int1 and fe_int2.
- clocks: the clock used by the core
- clock-names: the names of the clock listed in the clocks property. These are
	"ethif", "esw", "gp2", "gp1"
- power-domains: phandle to the power domain that the ethernet is part of
- resets: Should contain a phandle to the ethsys reset signal
- reset-names: Should contain the reset signal name "eth"
- mediatek,ethsys: phandle to the syscon node that handles the port setup
- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
	and driver current

Optional properties:
- interrupt-parent: Should be the phandle for the interrupt controller
  that services interrupts for this device

* Ethernet MAC node

Required properties:
- compatible: Should be "mediatek,eth-mac"
- reg: The number of the MAC
- phy-handle: see ethernet.txt file in the same directory and
	the phy-mode "trgmii" required being provided when reg
	is equal to 0 and the MAC uses fixed-link to connect
	with internal switch such as MT7530.

Example:

eth: ethernet@1b100000 {
	compatible = "mediatek,mt7623-eth";
	reg = <0 0x1b100000 0 0x20000>;
	clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
		 <&ethsys CLK_ETHSYS_ESW>,
		 <&ethsys CLK_ETHSYS_GP2>,
		 <&ethsys CLK_ETHSYS_GP1>;
	clock-names = "ethif", "esw", "gp2", "gp1";
	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
		      GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
		      GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
	reset-names = "eth";
	mediatek,ethsys = <&ethsys>;
	mediatek,pctl = <&syscfg_pctl_a>;
	#address-cells = <1>;
	#size-cells = <0>;

	gmac1: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-handle = <&phy0>;
	};

	gmac2: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-handle = <&phy1>;
	};

	mdio-bus {
		phy0: ethernet-phy@0 {
			reg = <0>;
			phy-mode = "rgmii";
		};

		phy1: ethernet-phy@1 {
			reg = <1>;
			phy-mode = "rgmii";
		};
	};
};
Commit	Line	Data
58ff9865 JC	1	MediaTek Frame Engine Ethernet controller
	2	=========================================
	3
	4	The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
	5	have dual GMAC each represented by a child node..
	6
	7	* Ethernet controller node
	8
	9	Required properties:
	10	- compatible: Should be "mediatek,mt7623-eth"
	11	- reg: Address and length of the register set for the device
f1d0540d JC	12	- interrupts: Should contain the three frame engines interrupts in numeric
f1d0540d JC	13	order. These are fe_int0, fe_int1 and fe_int2.
58ff9865 JC	14	- clocks: the clock used by the core
	15	- clock-names: the names of the clock listed in the clocks property. These are
	16	"ethif", "esw", "gp2", "gp1"
	17	- power-domains: phandle to the power domain that the ethernet is part of
	18	- resets: Should contain a phandle to the ethsys reset signal
	19	- reset-names: Should contain the reset signal name "eth"
	20	- mediatek,ethsys: phandle to the syscon node that handles the port setup
	21	- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
	22	and driver current
	23
	24	Optional properties:
	25	- interrupt-parent: Should be the phandle for the interrupt controller
	26	that services interrupts for this device
58ff9865 JC	27
	28	* Ethernet MAC node
	29
	30	Required properties:
	31	- compatible: Should be "mediatek,eth-mac"
	32	- reg: The number of the MAC
b8853965 SW	33	- phy-handle: see ethernet.txt file in the same directory and
	34	the phy-mode "trgmii" required being provided when reg
	35	is equal to 0 and the MAC uses fixed-link to connect
7f8c2865	36	with internal switch such as MT7530.
58ff9865 JC	37
	38	Example:
	39
	40	eth: ethernet@1b100000 {
	41	compatible = "mediatek,mt7623-eth";
	42	reg = <0 0x1b100000 0 0x20000>;
	43	clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
	44	<&ethsys CLK_ETHSYS_ESW>,
	45	<&ethsys CLK_ETHSYS_GP2>,
	46	<&ethsys CLK_ETHSYS_GP1>;
	47	clock-names = "ethif", "esw", "gp2", "gp1";
f1d0540d JC	48	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
	49	GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
	50	GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
58ff9865 JC	51	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	52	resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
	53	reset-names = "eth";
	54	mediatek,ethsys = <&ethsys>;
	55	mediatek,pctl = <&syscfg_pctl_a>;
	56	#address-cells = <1>;
	57	#size-cells = <0>;
	58
	59	gmac1: mac@0 {
	60	compatible = "mediatek,eth-mac";
	61	reg = <0>;
	62	phy-handle = <&phy0>;
	63	};
	64
	65	gmac2: mac@1 {
	66	compatible = "mediatek,eth-mac";
	67	reg = <1>;
	68	phy-handle = <&phy1>;
	69	};
	70
	71	mdio-bus {
	72	phy0: ethernet-phy@0 {
	73	reg = <0>;
	74	phy-mode = "rgmii";
	75	};
	76
	77	phy1: ethernet-phy@1 {
	78	reg = <1>;
	79	phy-mode = "rgmii";
	80	};
	81	};
	82	};