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a1c76734 YS |
1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: "http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#" | |
5 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | |
6 | ||
7 | title: Renesas SDHI SD/MMC controller | |
8 | ||
9 | maintainers: | |
10 | - Wolfram Sang <wsa+renesas@sang-engineering.com> | |
11 | ||
a1c76734 YS |
12 | properties: |
13 | compatible: | |
14 | oneOf: | |
15 | - items: | |
16 | - const: renesas,sdhi-sh73a0 # R-Mobile APE6 | |
17 | - items: | |
18 | - const: renesas,sdhi-r7s72100 # RZ/A1H | |
19 | - items: | |
20 | - const: renesas,sdhi-r7s9210 # SH-Mobile AG5 | |
21 | - items: | |
22 | - const: renesas,sdhi-r8a73a4 # R-Mobile APE6 | |
23 | - items: | |
24 | - const: renesas,sdhi-r8a7740 # R-Mobile A1 | |
25 | - items: | |
26 | - enum: | |
27 | - renesas,sdhi-r8a7778 # R-Car M1 | |
28 | - renesas,sdhi-r8a7779 # R-Car H1 | |
29 | - const: renesas,rcar-gen1-sdhi # R-Car Gen1 | |
30 | - items: | |
31 | - enum: | |
32 | - renesas,sdhi-r8a7742 # RZ/G1H | |
33 | - renesas,sdhi-r8a7743 # RZ/G1M | |
34 | - renesas,sdhi-r8a7744 # RZ/G1N | |
35 | - renesas,sdhi-r8a7745 # RZ/G1E | |
36 | - renesas,sdhi-r8a77470 # RZ/G1C | |
37 | - renesas,sdhi-r8a7790 # R-Car H2 | |
38 | - renesas,sdhi-r8a7791 # R-Car M2-W | |
39 | - renesas,sdhi-r8a7792 # R-Car V2H | |
40 | - renesas,sdhi-r8a7793 # R-Car M2-N | |
41 | - renesas,sdhi-r8a7794 # R-Car E2 | |
42 | - const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1 | |
43 | - items: | |
44 | - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP) | |
45 | - items: | |
46 | - enum: | |
bfadee45 BD |
47 | - renesas,sdhi-r8a774a1 # RZ/G2M |
48 | - renesas,sdhi-r8a774b1 # RZ/G2N | |
49 | - renesas,sdhi-r8a774c0 # RZ/G2E | |
50 | - renesas,sdhi-r8a774e1 # RZ/G2H | |
51 | - renesas,sdhi-r8a7795 # R-Car H3 | |
52 | - renesas,sdhi-r8a7796 # R-Car M3-W | |
53 | - renesas,sdhi-r8a77961 # R-Car M3-W+ | |
54 | - renesas,sdhi-r8a77965 # R-Car M3-N | |
55 | - renesas,sdhi-r8a77970 # R-Car V3M | |
56 | - renesas,sdhi-r8a77980 # R-Car V3H | |
57 | - renesas,sdhi-r8a77990 # R-Car E3 | |
58 | - renesas,sdhi-r8a77995 # R-Car D3 | |
59 | - renesas,sdhi-r8a779a0 # R-Car V3U | |
60 | - renesas,sdhi-r9a07g044 # RZ/G2{L,LC} | |
a1c76734 YS |
61 | - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 |
62 | ||
63 | reg: | |
64 | maxItems: 1 | |
65 | ||
66 | interrupts: | |
67 | minItems: 1 | |
68 | maxItems: 3 | |
69 | ||
bfadee45 | 70 | clocks: true |
a1c76734 | 71 | |
bfadee45 | 72 | clock-names: true |
a1c76734 YS |
73 | |
74 | dmas: | |
75 | minItems: 4 | |
76 | maxItems: 4 | |
77 | ||
78 | dma-names: | |
79 | minItems: 4 | |
80 | maxItems: 4 | |
81 | items: | |
82 | enum: | |
83 | - tx | |
84 | - rx | |
85 | ||
86 | power-domains: | |
87 | maxItems: 1 | |
88 | ||
89 | resets: | |
90 | maxItems: 1 | |
91 | ||
92 | pinctrl-0: | |
93 | minItems: 1 | |
94 | maxItems: 2 | |
95 | ||
96 | pinctrl-1: | |
97 | maxItems: 1 | |
98 | ||
4aba5dc7 | 99 | pinctrl-names: true |
a1c76734 YS |
100 | |
101 | max-frequency: true | |
102 | ||
4aba5dc7 BD |
103 | allOf: |
104 | - $ref: "mmc-controller.yaml" | |
105 | ||
bfadee45 BD |
106 | - if: |
107 | properties: | |
108 | compatible: | |
109 | contains: | |
110 | const: renesas,sdhi-r9a07g044 | |
111 | then: | |
112 | properties: | |
113 | clocks: | |
114 | items: | |
115 | - description: IMCLK, SDHI channel main clock1. | |
217c7d18 BD |
116 | - description: CLK_HS, SDHI channel High speed clock which operates |
117 | 4 times that of SDHI channel main clock1. | |
bfadee45 BD |
118 | - description: IMCLK2, SDHI channel main clock2. When this clock is |
119 | turned off, external SD card detection cannot be | |
120 | detected. | |
bfadee45 BD |
121 | - description: ACLK, SDHI channel bus clock. |
122 | clock-names: | |
123 | items: | |
217c7d18 BD |
124 | - const: core |
125 | - const: clkh | |
126 | - const: cd | |
bfadee45 BD |
127 | - const: aclk |
128 | required: | |
129 | - clock-names | |
130 | - resets | |
131 | else: | |
e051025e WS |
132 | if: |
133 | properties: | |
134 | compatible: | |
135 | contains: | |
136 | enum: | |
137 | - renesas,rcar-gen2-sdhi | |
138 | - renesas,rcar-gen3-sdhi | |
139 | then: | |
140 | properties: | |
141 | clocks: | |
142 | minItems: 1 | |
143 | maxItems: 3 | |
144 | clock-names: | |
145 | minItems: 1 | |
146 | uniqueItems: true | |
147 | items: | |
148 | - const: core | |
149 | - enum: [ clkh, cd ] | |
150 | - const: cd | |
151 | else: | |
152 | properties: | |
153 | clocks: | |
154 | minItems: 1 | |
155 | maxItems: 2 | |
156 | clock-names: | |
157 | minItems: 1 | |
158 | items: | |
159 | - const: core | |
160 | - const: cd | |
bfadee45 | 161 | |
4aba5dc7 BD |
162 | - if: |
163 | properties: | |
164 | compatible: | |
165 | contains: | |
166 | const: renesas,sdhi-mmc-r8a77470 | |
167 | then: | |
168 | properties: | |
169 | pinctrl-names: | |
170 | items: | |
171 | - const: state_uhs | |
172 | else: | |
173 | properties: | |
174 | pinctrl-names: | |
175 | minItems: 1 | |
176 | items: | |
177 | - const: default | |
178 | - const: state_uhs | |
179 | ||
180 | - if: | |
181 | properties: | |
182 | compatible: | |
183 | contains: | |
184 | enum: | |
185 | - renesas,sdhi-r7s72100 | |
186 | - renesas,sdhi-r7s9210 | |
187 | then: | |
188 | required: | |
189 | - clock-names | |
190 | description: | |
191 | The internal card detection logic that exists in these controllers is | |
192 | sectioned off to be run by a separate second clock source to allow | |
193 | the main core clock to be turned off to save power. | |
194 | ||
a1c76734 YS |
195 | required: |
196 | - compatible | |
197 | - reg | |
198 | - interrupts | |
199 | - clocks | |
200 | - power-domains | |
201 | ||
a1c76734 YS |
202 | unevaluatedProperties: false |
203 | ||
204 | examples: | |
205 | - | | |
206 | #include <dt-bindings/clock/r8a7790-cpg-mssr.h> | |
207 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
208 | #include <dt-bindings/power/r8a7790-sysc.h> | |
209 | ||
210 | sdhi0: mmc@ee100000 { | |
211 | compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; | |
212 | reg = <0xee100000 0x328>; | |
213 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; | |
214 | clocks = <&cpg CPG_MOD 314>; | |
215 | dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; | |
216 | dma-names = "tx", "rx", "tx", "rx"; | |
217 | max-frequency = <195000000>; | |
218 | power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; | |
219 | resets = <&cpg 314>; | |
220 | }; | |
221 | ||
222 | sdhi1: mmc@ee120000 { | |
223 | compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; | |
224 | reg = <0xee120000 0x328>; | |
225 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; | |
226 | clocks = <&cpg CPG_MOD 313>; | |
227 | dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>; | |
228 | dma-names = "tx", "rx", "tx", "rx"; | |
229 | max-frequency = <195000000>; | |
230 | power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; | |
231 | resets = <&cpg 313>; | |
232 | }; | |
233 | ||
234 | sdhi2: mmc@ee140000 { | |
235 | compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; | |
236 | reg = <0xee140000 0x100>; | |
237 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; | |
238 | clocks = <&cpg CPG_MOD 312>; | |
239 | dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; | |
240 | dma-names = "tx", "rx", "tx", "rx"; | |
241 | max-frequency = <97500000>; | |
242 | power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; | |
243 | resets = <&cpg 312>; | |
244 | }; | |
245 | ||
246 | sdhi3: mmc@ee160000 { | |
247 | compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; | |
248 | reg = <0xee160000 0x100>; | |
249 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; | |
250 | clocks = <&cpg CPG_MOD 311>; | |
251 | dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; | |
252 | dma-names = "tx", "rx", "tx", "rx"; | |
253 | max-frequency = <97500000>; | |
254 | power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; | |
255 | resets = <&cpg 311>; | |
256 | }; |