Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[linux-2.6-block.git] / Documentation / devicetree / bindings / mmc / mmc.txt
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1These properties are common to multiple MMC host controllers. Any host
2that requires the respective functionality should implement them using
3these definitions.
4
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5Interpreted by the OF core:
6- reg: Registers location and length.
7- interrupts: Interrupts used by the MMC controller.
8
abe1e05d 9Card detection:
b477426e 10If no property below is supplied, host native card detect is used.
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11Only one of the properties in this section should be supplied:
12 - broken-cd: There is no card detection available; polling must be used.
13 - cd-gpios: Specify GPIOs for card detection, see gpio binding
14 - non-removable: non-removable slot (like eMMC); assume always present.
15
7f217794 16Optional properties:
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17- bus-width: Number of data lines, can be <1>, <4>, or <8>. The default
18 will be <1> if the property is absent.
ed3efc1c 19- wp-gpios: Specify GPIOs for write protection, see gpio binding
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20- cd-inverted: when present, polarity on the CD line is inverted. See the note
21 below for the case, when a GPIO is used for the CD line
22- wp-inverted: when present, polarity on the WP line is inverted. See the note
23 below for the case, when a GPIO is used for the WP line
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24- disable-wp: When set no physical WP line is present. This property should
25 only be specified when the controller has a dedicated write-protect
26 detection logic. If a GPIO is always used for the write-protect detection
27 logic it is sufficient to not specify wp-gpios property in the absence of a WP
28 line.
7f217794 29- max-frequency: maximum operating clock frequency
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30- no-1-8-v: when present, denotes that 1.8v card voltage is not supported on
31 this system, even if the controller claims it is.
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32- cap-sd-highspeed: SD high-speed timing is supported
33- cap-mmc-highspeed: MMC high-speed timing is supported
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34- sd-uhs-sdr12: SD UHS SDR12 speed is supported
35- sd-uhs-sdr25: SD UHS SDR25 speed is supported
36- sd-uhs-sdr50: SD UHS SDR50 speed is supported
37- sd-uhs-sdr104: SD UHS SDR104 speed is supported
38- sd-uhs-ddr50: SD UHS DDR50 speed is supported
2fdb6e2d 39- cap-power-off-card: powering off the card is safe
794f1578 40- cap-mmc-hw-reset: eMMC hardware reset is supported
2fdb6e2d 41- cap-sdio-irq: enable SDIO IRQ signalling on this interface
5a36d6bc 42- full-pwr-cycle: full power cycle of the card is supported
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43- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
44- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
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45- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
46- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
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47- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported
48- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported
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49- dsr: Value the card's (optional) Driver Stage Register (DSR) should be
50 programmed with. Valid range: [0 .. 0xffff].
7f217794 51
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52*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
53polarity properties, we have to fix the meaning of the "normal" and "inverted"
54line levels. We choose to follow the SDHCI standard, which specifies both those
55lines as "active low." Therefore, using the "cd-inverted" property means, that
56the CD line is active high, i.e. it is high, when a card is inserted. Similar
57logic applies to the "wp-inverted" property.
58
59CD and WP lines can be implemented on the hardware in one of two ways: as GPIOs,
60specified in cd-gpios and wp-gpios properties, or as dedicated pins. Polarity of
61dedicated pins can be specified, using *-inverted properties. GPIO polarity can
62also be specified using the OF_GPIO_ACTIVE_LOW flag. This creates an ambiguity
63in the latter case. We choose to use the XOR logic for GPIO CD and WP lines.
64This means, the two properties are "superimposed," for example leaving the
65OF_GPIO_ACTIVE_LOW flag clear and specifying the respective *-inverted
66property results in a double-inversion and actually means the "normal" line
67polarity is in effect.
68
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69Optional SDIO properties:
70- keep-power-in-suspend: Preserves card power during a suspend/resume cycle
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71- wakeup-source: Enables wake up of host system on SDIO IRQ assertion
72 (Legacy property supported: "enable-sdio-wakeup")
e5d0e9c5 73
a31edf1e 74
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75MMC power sequences:
76--------------------
77
78System on chip designs may specify a specific MMC power sequence. To
79successfully detect an (e)MMC/SD/SDIO card, that power sequence must be
80maintained while initializing the card.
81
82Optional property:
83- mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*"
84 for documentation of MMC power sequence bindings.
85
86
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87Use of Function subnodes
88------------------------
89
90On embedded systems the cards connected to a host may need additional
91properties. These can be specified in subnodes to the host controller node.
92The subnodes are identified by the standard 'reg' property.
93Which information exactly can be specified depends on the bindings for the
94SDIO function driver for the subnode, as specified by the compatible string.
95
96Required host node properties when using function subnodes:
97- #address-cells: should be one. The cell is the slot id.
98- #size-cells: should be zero.
99
100Required function subnode properties:
101- compatible: name of SDIO function following generic names recommended practice
102- reg: Must contain the SDIO function number of the function this subnode
103 describes. A value of 0 denotes the memory SD function, values from
104 1 to 7 denote the SDIO functions.
105
106
107Examples
108--------
109
110Basic example:
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111
112sdhci@ab000000 {
113 compatible = "sdhci";
114 reg = <0xab000000 0x200>;
115 interrupts = <23>;
116 bus-width = <4>;
117 cd-gpios = <&gpio 69 0>;
118 cd-inverted;
119 wp-gpios = <&gpio 70 0>;
120 max-frequency = <50000000>;
e5d0e9c5 121 keep-power-in-suspend;
71a0151c 122 wakeup-source;
0e6d6332 123 mmc-pwrseq = <&sdhci0_pwrseq>
7f217794 124}
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125
126Example with sdio function subnode:
127
128mmc3: mmc@01c12000 {
129 #address-cells = <1>;
130 #size-cells = <0>;
131
132 pinctrl-names = "default";
133 pinctrl-0 = <&mmc3_pins_a>;
134 vmmc-supply = <&reg_vmmc3>;
135 bus-width = <4>;
136 non-removable;
0e6d6332 137 mmc-pwrseq = <&sdhci0_pwrseq>
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138 status = "okay";
139
140 brcmf: bcrmf@1 {
141 reg = <1>;
142 compatible = "brcm,bcm43xx-fmac";
143 interrupt-parent = <&pio>;
144 interrupts = <10 8>; /* PH10 / EINT10 */
145 interrupt-names = "host-wake";
146 };
147};