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26c188be ZLK |
1 | Imagination University Program MIPSfpga |
2 | ======================================= | |
3 | ||
4 | Under the Imagination University Program, a microAptiv UP core has been | |
5 | released for academic usage. | |
6 | ||
7 | As we are dealing with a MIPS core instantiated on an FPGA, specifications | |
8 | are fluid and can be varied in RTL. | |
9 | ||
10 | This binding document is provided as baseline guidance for the example | |
11 | project provided by IMG. | |
12 | ||
13 | The example project runs on the Nexys4DDR board by Digilent powered by | |
14 | the ARTIX-7 FPGA by Xilinx. | |
15 | ||
16 | Relevant details about the example project and the Nexys4DDR board: | |
17 | ||
18 | - microAptiv UP core m14Kc | |
19 | - 50MHz clock speed | |
20 | - 128Mbyte DDR RAM at 0x0000_0000 | |
21 | - 8Kbyte RAM at 0x1000_0000 | |
22 | - axi_intc at 0x1020_0000 | |
23 | - axi_uart16550 at 0x1040_0000 | |
24 | - axi_gpio at 0x1060_0000 | |
25 | - axi_i2c at 0x10A0_0000 | |
26 | - custom_gpio at 0x10C0_0000 | |
27 | - axi_ethernetlite at 0x10E0_0000 | |
28 | - 8Kbyte BootRAM at 0x1FC0_0000 | |
29 | ||
30 | Required properties: | |
31 | -------------------- | |
32 | - compatible: Must include "digilent,nexys4ddr","img,xilfpga". | |
33 | ||
34 | CPU nodes: | |
35 | ---------- | |
36 | A "cpus" node is required. Required properties: | |
37 | - #address-cells: Must be 1. | |
38 | - #size-cells: Must be 0. | |
39 | A CPU sub-node is also required for at least CPU 0. Required properties: | |
40 | - device_type: Must be "cpu". | |
41 | - compatible: Must be "mips,m14Kc". | |
42 | - reg: Must be <0>. | |
43 | - clocks: phandle to ext clock for fixed-clock received by MIPS core. | |
44 | ||
45 | Example: | |
46 | ||
47 | compatible = "img,xilfpga","digilent,nexys4ddr"; | |
48 | cpus { | |
49 | #address-cells = <1>; | |
50 | #size-cells = <0>; | |
51 | ||
52 | cpu0: cpu@0 { | |
53 | device_type = "cpu"; | |
54 | compatible = "mips,m14Kc"; | |
55 | reg = <0>; | |
56 | clocks = <&ext>; | |
57 | }; | |
58 | }; | |
59 | ||
60 | ext: ext { | |
61 | compatible = "fixed-clock"; | |
62 | #clock-cells = <0>; | |
63 | clock-frequency = <50000000>; | |
64 | }; | |
65 | ||
66 | Boot protocol: | |
67 | -------------- | |
68 | ||
69 | The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000. | |
70 | This is for easy reprogrammibility via JTAG. | |
71 | ||
72 | The BootRAM initializes the cache and the axi_uart peripheral. | |
73 | ||
74 | DDR initialization is already handled by a HW IP block. | |
75 | ||
76 | When the example project bitstream is loaded, the cpu_reset button | |
77 | needs to be pressed. | |
78 | ||
79 | The bootram initializes the cache and axi_uart. | |
80 | Then outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board. | |
81 | ||
82 | At this point, the board is ready to load the Linux kernel | |
83 | vmlinux file via JTAG. |