[linux-2.6-block.git] / Documentation / devicetree / bindings / memory-controllers / mediatek,smi-common.txt

SMI (Smart Multimedia Interface) Common

The hardware block diagram please check bindings/iommu/mediatek,iommu.txt

Mediatek SMI have two generations of HW architecture, mt8173 uses the second
generation of SMI HW while mt2701 uses the first generation HW of SMI.

There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
for generation 1, the register is at smi ao base(smi always on register
base). Besides that, the smi async clock should be prepared and enabled for
SMI generation 1 to transform the smi clock into emi clock domain, but that is
not needed for SMI generation 2.

Required properties:
- compatible : must be one of :
	"mediatek,mt2701-smi-common"
	"mediatek,mt8173-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
  for generation 2 smi HW as follows:
  - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
	    the register.
  - "smi" : It's the clock for transfer data and command.
	    They may be the same if both source clocks are the same.
  - "async" : asynchronous clock, it help transform the smi clock into the emi
	      clock domain, this clock is only needed by generation 1 smi HW.

Example:
	smi_common: smi@14022000 {
		compatible = "mediatek,mt8173-smi-common";
		reg = <0 0x14022000 0 0x1000>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		clocks = <&mmsys CLK_MM_SMI_COMMON>,
			 <&mmsys CLK_MM_SMI_COMMON>;
		clock-names = "apb", "smi";
	};
Commit	Line	Data
fb6e2cee YW	1	SMI (Smart Multimedia Interface) Common
	2
	3	The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
	4
7e42626a HZ	5	Mediatek SMI have two generations of HW architecture, mt8173 uses the second
	6	generation of SMI HW while mt2701 uses the first generation HW of SMI.
	7
	8	There's slight differences between the two SMI, for generation 2, the
	9	register which control the iommu port is at each larb's register base. But
	10	for generation 1, the register is at smi ao base(smi always on register
	11	base). Besides that, the smi async clock should be prepared and enabled for
	12	SMI generation 1 to transform the smi clock into emi clock domain, but that is
	13	not needed for SMI generation 2.
	14
fb6e2cee	15	Required properties:
7e42626a HZ	16	- compatible : must be one of :
	17	"mediatek,mt2701-smi-common"
	18	"mediatek,mt8173-smi-common"
fb6e2cee YW	19	- reg : the register and size of the SMI block.
	20	- power-domains : a phandle to the power domain of this local arbiter.
	21	- clocks : Must contain an entry for each entry in clock-names.
7e42626a HZ	22	- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
7e42626a HZ	23	for generation 2 smi HW as follows:
fb6e2cee YW	24	- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
	25	the register.
	26	- "smi" : It's the clock for transfer data and command.
7e42626a HZ	27	They may be the same if both source clocks are the same.
	28	- "async" : asynchronous clock, it help transform the smi clock into the emi
	29	clock domain, this clock is only needed by generation 1 smi HW.
fb6e2cee YW	30
	31	Example:
	32	smi_common: smi@14022000 {
	33	compatible = "mediatek,mt8173-smi-common";
	34	reg = <0 0x14022000 0 0x1000>;
	35	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	36	clocks = <&mmsys CLK_MM_SMI_COMMON>,
	37	<&mmsys CLK_MM_SMI_COMMON>;
	38	clock-names = "apb", "smi";
	39	};